If permitted, please upload a project: (1). Build->Clean; (2) File->Create workspace bundle->Minimal; (3) to reduce file size delete "Generated_source" folder in newly created archive.
I believe that the issue arises due to wc1/wc2 outputs. These are direct output from DMA nrq output, which is not in sync with BUS_CLK. Try to add a Sync component to it, synchronized to the BUS_CLK.
Thanks for the SYNC suggestion on the WC output. That did the trick, no timing warnings now. Thanks very much.