5 Replies Latest reply on Mar 28, 2019 2:37 AM by SrinathS_16

    synchronous slave FIFO with external PCLK

    aswac_3439426

      Hi,

      I am new to the FX3 and need help setting up the FX3 as a slave FIFO with an external clock. I have the superspeed kit, and I am using John Hyde's book for guidance and examples. My application ( high-speed ADC) is very close to one of his examples in the book (GPIF example 4) except for the direction of the clock.

      Other than modifying it in the GPIF designer and including the new header file, do I need to make changes to the firmware?

      I can probe and confirm the FX3 is not outputing any clock, but the DMA_ready flag for some reason is never asserted in this case.

      How shall I approach this issue?

       

      Thanks,

      Ashraf

        • 1. Re: synchronous slave FIFO with external PCLK
          SrinathS_16

          Hello Ashraf,

           

          - There are no other modifications required other than that in the GPIF II designer.

          - Please check if the thread that you are using in the GPIF II corresponds to the DMA ready flag that you are checking.

          - Also, check if you are able to perform any read/write with the GPIF II thread in use.

           

          Best regards,

          Srinath S

          • 2. Re: synchronous slave FIFO with external PCLK
            aswac_3439426

            Hello Srinath,

             

            Thank you for your reply. Please bear with me as I am new to this chip.

            First I wanted to clarify, this is not the FIFO slave example that came with the SDK, but one example in the book by John Hyde (design by example). some of the signal names are different.

            The closest example to what I need had a FX3 as FIFO slave, and controlling the data with a DMA ready and watermark signals. All I did was open this project in the GPIF designer and switch the direction of the clock. I did notice 2 things:

            - the DMA ready was active low, which seems reverse of the example polarity. I will try switching the polarity and see how it goes.

            - the interface type was set as master

            I only see 3 registers different for the GPIF config, and I am reading the reference manual to decipher these differences.

             

            Thanks,

            Ashraf

            • 3. Re: synchronous slave FIFO with external PCLK
              SrinathS_16

              Hello Ashraf,

               

              - What is the external source of the PCLK that you are using and its frequency?

              - In case you have access to the UART pins of FX3, please collect the UART logs to check the state of the GPIF II state machine. The CyU3PGpifGetSMState() API can be used to obtain the current state of the GPIF II state machine.

              - Can you please share the entire firmware and GPIF II project for me to reproduce the issue at my end?

               

              Best regards,

              Srinath S

              • 4. Re: synchronous slave FIFO with external PCLK
                aswac_3439426

                Hi Srinath,

                 

                Thanks for these suggestions. the PCLK source is an FPGA and is 20MHz. I am still troubleshooting the FPGA side of things, but I believe I managed to send data to the FX3 FIFO. I did so by manually setting the DMA flags. I believe I still have some bugs to fix to align GPIF and FGPA state machines.

                I have confirmed that I am sending data to the FIFO using the PC utility. I did notice that preceding the data, I get this fixed "pattern" of -269488145.

                I will post the the FW and GPIF project shortly.

                 

                Thank you,

                Ashraf

                • 5. Re: synchronous slave FIFO with external PCLK
                  SrinathS_16

                  Hello Ashraf,

                   

                  I have confirmed that I am sending data to the FIFO using the PC utility. I did notice that preceding the data, I get this fixed "pattern" of -269488145

                  >> Do you mean to say that you are able to receive data on the PC utility.

                   

                  DMA_Ready flag gets asserted when there is enough space on the buffer. For buffer space to be available, data needs to be read from the host. Please use the CyU3PGpifGetSMState() API to check if the firmware enters the state in which the data is read from the GPIF II interface.

                   

                  Also, attach the firmware and the GPIF II project files.

                   

                  Best regards,

                  Srinath S