Did you get any STA warnings? You can refer to the STA Report for maximum allowable frequency and to know if any potential timing problems exist.
Refer to the document below:
I checked for STA warnings and there were none. The timing violation happens because the Capture signal violates setup and hold timing because it is asynchronous to the logic clock and Creator has no way of knowing that so it wouldn't show in the report.
I set the Capture input pin to double-sync (the only choice other than transparent) and I am no longer getting hangs when checking the status register for setting of the Capture bit. This change does affect the timing I measure by a little but I can live with it. Fortunately the clock is 240 times faster than the signal on the Capture input so even if it causes a full two clock delay that is less than a percent of difference. Apparently trigger is not a synchronous signal because I am not seeing a problem with setup and hold on it so I am able to leave it set to transparent.