2 Replies Latest reply on Mar 11, 2019 8:22 AM by timoc_264486

    How to measure time between two asynchronus edges?

    timoc_264486

      I am trying to measure the time between two asynchronous rising edges. Here is the timer I am using:

       

      Ashampoo_Snap_Friday, March 8, 2019_15h46m03s_005_.png

      Pre_R_ To_CPU always occurs first then Post_R_To_CPU happens and I need to measure the time in-between.

      It works OK sometimes but the read status register call frequently hangs. I believe the problem is caused by the capture and/trigger happening simultaneous to the bus clock which is causing a metastability which then causes the component to hang. If that is right then I am not sure how to avoid this problem because if I do anything to change the timing of Pre_R or Post_R then I change the measurement. BTW - these two signals occur in the 100kHz frequency range and I want clock to be as high of a frequency as possible to give me the greatest resolution possible. Ideas?

        • 1. Re: How to measure time between two asynchronus edges?
          EktaN_26

          Hello

           

          Did you get any STA warnings? You can refer to the STA Report for maximum allowable frequency and to know if any potential timing problems exist.

          Refer to the document below:

          https://www.cypress.com/file/179061/download

           

          Thanks

          • 2. Re: How to measure time between two asynchronus edges?
            timoc_264486

            I checked for STA warnings and there were none. The timing violation happens because the Capture signal violates setup and hold timing because it is asynchronous to the logic clock and Creator has no way of knowing that so it wouldn't show in the report.

             

            I set the Capture input pin to double-sync (the only choice other than transparent) and I am no longer getting hangs when checking the status register for setting of the Capture bit. This change does affect the timing I measure by a little but I can live with it. Fortunately the clock is 240 times faster than the signal on the Capture input so even if it causes a full two clock delay that is less than a percent of difference. Apparently trigger is not a synchronous signal because I am not seeing a problem with setup and hold on it so I am able to leave it set to transparent.

             

            Problem solved.