2 Replies Latest reply on Mar 5, 2019 7:30 AM by user_443952341

    I've got a large, constant delay in getting a shift out value out of a datapath operation, regardless of the given clock. Why?


      I'm designing a USB-based driver for WS2812 LEDs. As a part of the project I need to serialize some data but unfortunately the delay between entering a shifting operation in a datapath and getting a bit on the 'Shift Out' output is prohibitively large (26us). It doesn't deviate from this value by more than 1us, regardless of the speed of the clock I feed the datapath with. Also, I don't have any additional logic between the output I read and the datapath's shift out. Is this delay an intrinsic part of the datapath design? It seems really excessive, given the usual order of magnitude of propagation delays in the timing analysis (~30ns), and prevents me from operating the UDB component at periods longer than that 26us.