RXEMPTY# and RXFULL# asserted in the same time on CY7C9689A transceiver

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degac_4078881
Level 1
Level 1

Hi,

I develop an FPGA for a client which uses an CY7C9689A transceiver with

- FIFO activated,

- 4B/5B encoder/decoder enabled,

- 8-bit data (ans so 4-bit cmd).

The board drives by a ROBOCLOCK the following clocks :

- TXCLK at 25 MHz,

- RXCLK at 25 MHz,

- REFCLK at 12,5 MHz.

I have a stange behaviour in RX with long frame (about 1Mo).

Sometimes, there is a few data bytes loss.

In this labo test, the transmitter is an old taxi chip AM7968.

I drive RXEN# at '0' all the time excepted when I can not grab more data (it isn't the case here).

After investigation, we see the following behaviour :

sometimes we have in the same time RXEMPTY# and RXFULL# assertion without RXHALF# assertion, cf. snapshot pb_rxfull_CY7C9689A.png extracted from a Chipscope trace In this extract (clock chipscope = RXCLK), the data is here at 0x00 but same thing with other patterns.

The START command is 0x1.

As we have RXEMPTY# asserted, the FPGA grabs no data at this time.

pb_rxfull_CY7C9689A.png

My client asks to me to desactivate RXEN# when I see RXEMPTY# asserted, cf. snapshot rx_with_patch.png and then no issue, no loss we don't see then RXEMPTY# and RXFULL# asserted in the same time.

rx_with_patch.png

I don't understand why ?

Can you explain to me this behavior ?

Are there some constraints about phase between REFCLK and RXCLK ?

BR

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Roy_Liu
Moderator
Moderator
Moderator
5 comments on KBA First comment on KBA 10 questions asked

Need a better description of what you are trying to do here.  While the RX has a SHORT fifo, it is not infinite.  At the RX end of a link, there is no relationship between the phase of REFCLK and RXCLK.  REFCLK is only used (at the RX end of a link) to ensure that the receive PLL is within the allowed operating range. This is normally around +/- a few hundred PPM.  If the received bitstream is outside of the allowed limits, then the receiver will lock to the REFCLK and ignore the serial data stream.  If the RX FIFO is enabled (FIFOBYP* is HIGH), this output changes on the rising edge of the RXCLK input.

The description of having data continuous for millions of bytes is more concerned.  That is not possible in any FIFO mode to do this, UNLESS the data stream contains JK pairs that can be discarded.  If the RX FIFO is bypassed, then you can run continuous, but then the RXCLK is an output.

Also, as far as FIFO flags, there are three flags, and to understand what is going on we need to see the HALF flag too.

Roy Liu
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