2 Replies Latest reply on Mar 11, 2019 5:39 PM by RoyL_01

    RXEMPTY# and RXFULL# asserted in the same time on CY7C9689A transceiver

    degac_4078881

      Hi,

       

      I develop an FPGA for a client which uses an CY7C9689A transceiver with

      - FIFO activated,

      - 4B/5B encoder/decoder enabled,

      - 8-bit data (ans so 4-bit cmd).

       

      The board drives by a ROBOCLOCK the following clocks :

      - TXCLK at 25 MHz,

      - RXCLK at 25 MHz,

      - REFCLK at 12,5 MHz.

       

      I have a stange behaviour in RX with long frame (about 1Mo).

      Sometimes, there is a few data bytes loss.

       

      In this labo test, the transmitter is an old taxi chip AM7968.

      I drive RXEN# at '0' all the time excepted when I can not grab more data (it isn't the case here).

      After investigation, we see the following behaviour :

      sometimes we have in the same time RXEMPTY# and RXFULL# assertion without RXHALF# assertion, cf. snapshot pb_rxfull_CY7C9689A.png extracted from a Chipscope trace In this extract (clock chipscope = RXCLK), the data is here at 0x00 but same thing with other patterns.

      The START command is 0x1.

       

      As we have RXEMPTY# asserted, the FPGA grabs no data at this time.

      pb_rxfull_CY7C9689A.png

      My client asks to me to desactivate RXEN# when I see RXEMPTY# asserted, cf. snapshot rx_with_patch.png and then no issue, no loss we don't see then RXEMPTY# and RXFULL# asserted in the same time.

      rx_with_patch.png

      I don't understand why ?

       

      Can you explain to me this behavior ?

       

      Are there some constraints about phase between REFCLK and RXCLK ?

       

      BR