I thank for having had you show your design and think that it is very interesting.
It is a device to let you maintain an RUN state of COUNTER to have attracted
interest in particular.
I intend to perform an experiment for confirmation from now on.
I tried with following schematic.
But when I tried to set the period to 255, I got error saying that the allowed range is 1 to 254.
So I set the period to 254
On my oscilloscope
ch1 : cntr_reset
ch2 : comp
ch3 : ENABLE
ch4 : Pixel_clock
When I set compare value to 0
compare value = 10
compare value = 100
compare value = 254
compare value = 255
So, when I set the period to 254, the circuit seems to be working.
Meantime, with current PSoC Creator, I could not set the period to 255,
so may be setting the period to 255, which seems to be allowed earlier,
was the problem.
So I think we came as far as we could get with 8bit counter.
And if you really need 255 equality, we need a counter with more than 8bit width.
Probably using a 16bit mode or create a 9~bit UDB one.
Anyway, at least a good news is the counter itself seems working ;-)
I thank the people who answered. Thank you, MOTO. Thank you, JW.
As a result, this counter works definitely now in my environment. It was a difficult part
to think of the cause of COUNTER not having worked. The counter has begun to work
by decreasing system clock frequency. Because I used up UDB approximately 100%
by my design, it seemed to happen.
This clock signal does not exist in the connection diagram which I showed in this matter.
I will do the detailed report about this matter with another opportunity.
I helped that the inspection contents of all of you discovered a cause early.
Thank you again.