You have the S0, S1 and S2 lines for selecting the values for P, Q dividers for PLL1 which can generate upto 8 different frequency profiles from 000 to 111 values for the select lines respectively.
S2 is a general purpose input that is programmed to allow for two different frequency settings. Options that switches with this general purpose input are as follows: the frequency of PLL1, the output divider of CLKB, and the output divider of CLKA.
The two frequency settings are contained within an eight-row frequency table. The values of SCLK (S1) and SDAT (S0) pins are latched during start up and used as the other two indexes into this array. CLKA and CLKB have seven-bit dividers that point to one of the two programmable settings (register 0 and register 1). Both clocks share a single register control and both must be set to register 0, or both must be set to register 1.
While using the Cyberclocks software you can go to advanced mode tab. There you can see a bit viewer tab where you fill find all the register details you will require.