Should we run the CC line status through the ADC code inside the CCG and get output that way for Legacy connections that present Rp 56K
1. As per my comments in the additional threads you have filled, I guess this threads is one of question from same project. I have take a look the waveform you have attached in the threads, it seems the CC is still toggling with a small volt on the CC line. Based on your design,
a. Could you please kindly measure the CC voltage on the CC1 or CC2?
>> If the cable you have been attached is Type-C plug to Type-A plug, and CCG3PA is power sink role, please assure that the CC have Rp present on CC line and VBUS shall be enabled by Type-A host side. (From the wavefrom, the Power source is not enable VBUS with 5V.)
b. Could you please kindly check whether the VBUS is enabled (Refer above comments)? (As per Type-C SPEC V1.3 Table 4-25 VBUS and VCONN Timing Parameters, tVBUSon, the max time is 275ms. )