I see 4 clocks delay between the input and output. Somewhere in the DelSig-ADC's datasheet is mentioned that it needs 4 clocks to "prime".
Since the output (VDAC8) is already 8-bit, try to reduce ADC's resolution to 8-bit and rise sampling frequency to the max to improve frequency response.
Due to intgrating nature of DelSig-ADC, there will always be a delay. It's intended frequency domain is <20kHz. For 100+kHz domain consider using SAR-ADC.
Thank you for the response! I will take a closer look into the SAR-ADC for my application.
With kind regards,