1 Reply Latest reply on Mar 19, 2019 2:38 AM by SrinathS_16

    FX3 SPI Multiple 32Bit Transfers




      I am trying to find the SPI speed of multiple transfers.  I am currently using the SPI clk at 33MHz with a 32 bit transfer.  This operates correctly but the delay between multiple SPI transfers seems to be much longer than the transfer speed.


      1uS for transfer of packet using 32 bits.

      delay of 14uS for transfer of next packet.


      No delays between multiple transfers of packets just a loop of 10 32 bit transfers. I am seeing a long delay (14uS) after the first packet to the next packet from the SPI peripheral.  We are currently using register transfers for the SPI.


      1) What is the maximum speed of multiple transfers? back to back, 32 bit transfers out or in using SPI.

      2) What are some options for reducing the transfer delay with the library calls?

      3) Will using the DMA for SPI transfers reduce my delay between SPI packets?


      Thank you,


      Steve W.

        • 1. Re: FX3 SPI Multiple 32Bit Transfers

          Hello Steve,


          - Please let us know how you are implementing multiple SPI transfers back to back. Are you pulling the slave select HIGH after every 32 bit transaction? Are the status check and write enable commands issued after every 32 bit transaction? Please share the firmware code snippet if possible.

          - Using DMA will reduce the delay since it does not involve the CPU in the transfer path.


          EDIT: In case of register mode SPI transfers, the firmware needs to initiate the transfer every time which can cause delays. If your application requires transfer of large number of bytes of data, please use the SPI DMA mode.


          Best regards,

          Srinath S