1 Reply Latest reply on Feb 14, 2019 5:29 AM by SananyaM_56

    Reverse engineering CY7C68013 connections

    wokac_2711691

      I am building a GPS RF receiver using a  CY7C68013 chip to stream data to a computer. It is a modification of older design that uses GPIF mode.

      Is it possible to reverse engineer the hardware connections to the chip from this file:

      gr-gn3s/gpif.gpf at master · gnss-sdr/gr-gn3s · GitHub

      Both radio chips (my one and old design one) use 2- or 4-bit wide bus and a single 16.3MHz clock signal. Data bus connection is obvious for me. I suspest that the clock signal should be connected to IFCLK pin, but I am not sure.

      Can someone help me?

        • 1. Re: Reverse engineering CY7C68013 connections
          SananyaM_56

          Hello,

           

          You can check the block diagram from the file which gives information on the connections using the GPIF Designer application and also generate the gpif.c file. The application is present at the following installation path in the FX2LP DVK-

          <install directory>\Cypress\USB\CY3684_EZ-USB_FX2LP_DVK\1.1\GPIF_Designer

          Please let me know if you were looking for any other information from the older design?

           

          Best Regards,

          Sananya