3 Replies Latest reply on Feb 25, 2019 12:05 AM by VasanthR_91

    DelSig Gain Drift with External Reference




      we use 3 ppm/K external 1.024 V reference to drive P0.3 and P0.6 with 16-bit DelSig, Voltage Range = 1 V (ext ref).


      However since we have a multi-channel system, which requires MUXes (high-resistant switches) inside the PSoC analog routing matrix, we are forced to use the Buffered mode, which has specs (data-sheet page 88):


      • Gd: Buffered, buffer gain = 1, Range =±1.024 V, 16-bit mode: 50 ppm/K (max)
      • TCVos: Offset | Buffer gain = 1, 16-bit, Range = ±1.024 V: 1 uV/K (max)


      Our problem is this 50 ppm/K (max) drift, since it does not justify the use of the external reference, as it is the major contributor of the error, and the unbuffered ADC mode cannot be used due to too high impedance of the analog routing switches.


      and we have measured the gain drift, that includes 3 ppm/K (max) of the Vref, on a particular sample to be (negative):

      • -16.1 ppm/C  (measured as V_ADC - ReferenceVoltage)



      1. For the same analog routing configuration and working conditions, how much of this gain drift is expected to be different (dispersed) across different samples, and on long-term?
      2. Since we're using the external reference, do you see any possible way of compensating the gain drift with the external reference; as measuring it directly on some other pins is somewhat impractical (since the voltage may be at max and may saturate over, and it is not wise to add noise to the ref pins either), then the ext. Vref cannot be bypassed to some analog pins, or being internally divided, ... everything shows like it would require another external reference to sample this reference, or that internal reference is used and to sample external, however, when on same pins, bypass cap cannot be used, which would induce higher noise, and the other by-pass pins are already occupied in our case.


      BR Uros