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Hi,
I have read the HyperBus Memory Controller IP specification (HyperBus_Ctrl_IP_Spec_v2p40) and I have an important doubt.
In this document are mentioned AXI and AXI_LITE as interfaces for Control registers (Figure 2 and Figure 5)
This is confusing. AXI-LITE is a much more reduced protocol than AXI with support to fewer features, for instance AXI-LITE does not have burst support.
In Table 9 read/write transactions for Control Register Acces Port have burst size different than 0.
Shall I suppose that the connection with the controls registers is AXI?
Thank you
Solved! Go to Solution.
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Hello Guillem,
Please see below.
Shall I suppose that the connection with the controls registers is AXI?
Answer - Yes
Thank you and have a nice day
Regards,
Bushra
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Hello Guillem,
Thank you for contacting Cypress Community Forum. Currently we are reviewing the issue and will get back to you as soon as we find the resolution.
Have a wonderful day
Regards,
Bushra
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Hello Guillem,
Please see below.
Shall I suppose that the connection with the controls registers is AXI?
Answer - Yes
Thank you and have a nice day
Regards,
Bushra