FIgure 2 of AN61345 shows this diagram, which indicates that IFCLK is generated by the FPGA and fed to the FX2LP component:
In the context of Slave FIFO mode, is it also valid to generate the IFCLK within the Cypress FX2LP chip, feed it through the FX2LP's output buffer, and use it directly in the FPGA for the synchronous state machine? Are there any timing considerations I'm not aware of? This seems straightforward enough to me.
Yes that can also be done with Slave FIFO mode. You can set IFCONFIG register with internal clock enabled, output enabled and synchronous mode enabled for your requirement. Please refer to Section 9.2.3 in the Technical Reference Manual for more details on the register.