It is not recommended to toggle the capture signal at the rising edge of the clock as this will lead to metastability.
I understood this configuration (AN81623 Figure 22 and Figure 34) avoids STA warning but use is not recommended.
I think that it is better to modify this application note.
Thanks for your feedback
> It is not recommended to toggle the capture signal at the rising edge of the clock as this will lead to metastability.
I have a different opinion, as far as the circuit is designed in a "synchronized design" without "setup time violation" nor "hold time violation", all the data transition(s) will take place at the rising edge of system clock.
In the timing diagram above, which is not the timing chart of the circuit schematic, the lower blue rising edge should be aligned with the clock if it came through the "Sync" component. So in the picture above if the lower blue rising edge is aligned to the blue clock edge we will get 0x7F, and if the blue rising edge is aligned to the next clock rising edge, we will get 0x80.
So I hope that AN81623 has its reason to exist.
Thank you for your reply.
As far as the counter datasheet is concerned,
I am concerned because clock and capture do not describe the timing synchronized on the rising edge.
We are planning to acquire capture at falling edge so that it will not be a meta stable.
However, in the case of the SYNC component, the falling will be asynchronous, is not it?
We would like to synchronize to avoid STA warning, but handling of capture is difficult.
> I am concerned because clock and capture do not describe the timing synchronized on the rising edge.
Since I don't have access to the Cypress's internal information, I can only guess, but I'm hoping that any input signal of a counter should be synchronized on the rising edge of the clock. (except async reset or async preset)
But it may be good idea to use negative edge to stay in the safer side.
> However, in the case of the SYNC component, the falling will be asynchronous, is not it?
This is also another guess, but usually CDC (Clock Domain Crossing) sync is done by using a couple of DFFs
so the falling edge will also be synchronized with the sync-clock.
So although my info may not have been any help after all, I hope your project will be successful ;-)