1 Reply Latest reply on Jan 30, 2019 10:24 PM by himam_31

    DMA NRQ for SPI read always one byte early


      In the following setup:

      I'm sending two bytes and then read 10 back, as seen here:

      After the two bytes are sent, I clear the SPI Rx FIFO, which clears the DRQ to the Rx DMA channel.  I then transmit 10 dummy bytes to read 10 bytes back.  As you can see in the trace above, the Rx interrupt (driven by the DMA NRQ signal) occurs at the beginning of the last byte being clocked in, rather than at the actual completion of the transfer.


      I've tried this with different transfer sizes and this always happens one byte early.  The transfer does complete before I get around to handling it, so it effectively works, but I'd like to understand what's going on here and avoid future problems.