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Hi,
I try to configure a basic (just sleep mode) low power mode for the CYBLE-212006 BLE module. I started with the 100 projects in 100 days Project: "Day041_PSoC_4_BLE_Low_Power_Modes".
This is the important piece of code:
void HandleLowPowerMode(uint8 lpmSel)
{
#ifdef ENABLE_LOW_POWER_MODE
/* Local variable to store the status of BLESS Hardware block */
CYBLE_LP_MODE_T sleepMode;
CYBLE_BLESS_STATE_T blessState;
if (lpmSel == DEEPSLEEP)
{
...
}
else if (lpmSel == SLEEP)
{
/* Leave chip in Sleep mode */
/* Leave chip in Deep Sleep mode */
/* Put BLESS into Deep Sleep and check the return status */
sleepMode = CyBle_EnterLPM(CYBLE_BLESS_SLEEP);
/* Disable global interrupt to prevent changes from any other interrupt ISR */
CyGlobalIntDisable; <---------------------
/* Check the Status of BLESS */
blessState = CyBle_GetBleSsState();
if(sleepMode == CYBLE_BLESS_SLEEP)
{
if(blessState != CYBLE_BLESS_STATE_EVENT_CLOSE)
{
/* If BLE Event has not
* closed yet, then place CPU to Sleep */
#ifdef ENABLE_LED_NOTIFICATION
BLUE_Write(0);
BLUE_SetDriveMode(BLUE_DM_STRONG);
#endif
CySysPmSleep();
#ifdef ENABLE_LED_NOTIFICATION
BLUE_SetDriveMode(BLUE_DM_STRONG);
BLUE_Write(1);
#endif
}
}
/* Re-enable global interrupt mask after wakeup */
CyGlobalIntEnable;
}
else if (lpmSel == ACTIVE)
{
...
}
#endif
}
The code make sense and I think there are no problems to implement it. But why are the interrupts disabled before entering the SleepMode? Is it possible to enter the SleepMode without disabling the interrupts and using BLE? What does: "to prevent changes from any other interrupt ISR" mean? I'm using some critical peripherals (868 MHz radio cpu) and don't want to disable all isr's.
Thanks!
Solved! Go to Solution.
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By critical section here , I assume the processor is in low power state ( waiting for interrupt source to wakeup). The interrupt request line (IRQ) first goes to wakeup interrupt controller (WIC) where it makes the processor to wake up from low power state and as soon as it wakes up we will enable the interrupt and the respective interrupt ISR will be executed. Please refer the below document for more details on this.
https://www.cypress.com/file/127121/download
-Gyan
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Hi Pascal,
While entering into the low power modes of device there are some register writes which happens to configure the clocking systems and other peripheral states. If the interrupts are enabled during this time spam and if by any chance any interrupt occurs it may cause the processor to enter into any unknown state. To prevent this it is recommended to disable the interrupts while entering into the low power states.
These APIs puts the processor in low power modes only when there is no activity and should not cause any problem by disabling the interrupts while entering into low power modes.
-Gyan
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Hi Gyan,
thanks for your reply!
What happens with isr events if the cpu is in a critical section? Are they nested and called after the cpu leaves the critical section or are they lost?
Best regards!
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By critical section here , I assume the processor is in low power state ( waiting for interrupt source to wakeup). The interrupt request line (IRQ) first goes to wakeup interrupt controller (WIC) where it makes the processor to wake up from low power state and as soon as it wakes up we will enable the interrupt and the respective interrupt ISR will be executed. Please refer the below document for more details on this.
https://www.cypress.com/file/127121/download
-Gyan