While entering into the low power modes of device there are some register writes which happens to configure the clocking systems and other peripheral states. If the interrupts are enabled during this time spam and if by any chance any interrupt occurs it may cause the processor to enter into any unknown state. To prevent this it is recommended to disable the interrupts while entering into the low power states.
These APIs puts the processor in low power modes only when there is no activity and should not cause any problem by disabling the interrupts while entering into low power modes.
thanks for your reply!
What happens with isr events if the cpu is in a critical section? Are they nested and called after the cpu leaves the critical section or are they lost?
By critical section here , I assume the processor is in low power state ( waiting for interrupt source to wakeup). The interrupt request line (IRQ) first goes to wakeup interrupt controller (WIC) where it makes the processor to wake up from low power state and as soon as it wakes up we will enable the interrupt and the respective interrupt ISR will be executed. Please refer the below document for more details on this.