1 2 Previous Next 20 Replies Latest reply on May 20, 2019 2:13 AM by inanity407_2949331

    FX3 GPIF CRC engine (again)

    inanity407_2949331

      Hi everyone!

       

      Unfortunately this topic was locked.

       

      I need to control data integrity of FX3 GPIF bus in PP mode. There is some CRC engine, but it is not documented at all.

       

      I tried to make it work and I have some successful results:

      I can configure this CRC over GPIF_CRC_CONFIG and GPIF_CRC_DATA regs.

      First set ENABLE = 1 (bit 31) of GPIF_CRC_CONFIG and INITIAL_VALUE[15:0] = 0xFFFF of GPIF_CRC_DATA reg.

      Manually changing bits in GPIF FSM configuration I could make it work in write direction (from FX3 to AP).

      I used BETA_INIT_CRC bit to reset init value to previously defined INITIAL_VALUE[15:0] and BETA_CALC_CRC to make calculation.

      Calculated CRC appears in CRC_VALUE[15:0]  of GPIF_CRC_DATA reg.

      I figured out that "CRC-16/CCITT-FALSE" with params poly = 0x1021 is used in hardware.

       

       

      QUESTION: I run GPIF in 32-bit mode, but that CRC16 does not use higher 16 bits of bus during calculation. In other words only lower 16-bits

      are CRC controlled. How to make it work in 32-bit mode, not 16-bit? What am I doing wrong?

       

      P.S. I don't need working example, just explain it here please. I need it very much. Thank you!

       

      Best regards

        • 1. Re: FX3 GPIF CRC engine (again)
          inanity407_2949331

          Following EZ-USB® FX3™ Technical Reference Manual document at page 358 one can find:

          BYTE_ENDIAN - Indicates the order in which bytes in a 32-bit word are brought through the CRC shift register. This is independent from the endianness of the interface.

          Looks like CRC engine works with 32-bit words.

           

          I guess your engineers have HDL sources that can reveal the way this CRC works. That shouldn't be a problem for you to answer my question.

           

          Thanks in advance

          • 2. Re: FX3 GPIF CRC engine (again)
            KeerthyV_76

            The CRC calculation is controlled by betas. On beta initialize_crc (CYU3GPIF_BETA_INIT_CRC), the CRC is initialized to the value programmed in GPIF_CRC_DATA.INITIAL_VALUE. The CRC is calculated when beta calculate_crc (CYU3GPIF_BETA_CALC_CRC)is set and read (CYU3GPIF_BETA_POP_RQ ) or write (CYU3GPIF_BETA_PUSH_WQ) is done. The calculated CRC is reflected in GPIF_CRC_DATA.CRC_VALUE.

             

            • The calculated CRC is transmitted when beta use_crc (CYU3GPIF_BETA_USE_CRC) is set and alpha update_dout (CYU3GPIF_ALPHA_UPD_DOUT) is asserted.
            • The incoming CRC is sampled when beta use_crc (CYU3GPIF_BETA_USE_CRC) is set and beta wq_push (CYU3GPIF_BETA_PUSH_WQ) is asserted.
            1 of 1 people found this helpful
            • 3. Re: FX3 GPIF CRC engine (again)
              inanity407_2949331

              Hi, KeerthyV_76

               

              This is incredibly useful information!

              I'm going to try make it work according to your explanations.

               

              Thank you!

               

              P.S. Please don't lock this topic for a while. I will mark right anwer as soon as possible.

              • 4. Re: FX3 GPIF CRC engine (again)
                inanity407_2949331

                Hi, KeerthyV_76

                 

                It seems to be not so easy, as I supposed.

                 

                On beta initialize_crc (CYU3GPIF_BETA_INIT_CRC), the CRC is initialized to the value programmed in GPIF_CRC_DATA.INITIAL_VALUE.

                Initialization works fine.

                The CRC is calculated when beta calculate_crc (CYU3GPIF_BETA_CALC_CRC) is set and read (CYU3GPIF_BETA_POP_RQ ) or write (CYU3GPIF_BETA_PUSH_WQ) is done. The calculated CRC is reflected in GPIF_CRC_DATA.CRC_VALUE.

                I can see that GPIF_CRC_DATA.CRC_VALUE changes on write, but I can't do the same for the read. It doesn't calculate it for read. Maybe some GPIF configuration registers are not set properly? I tried to set DOUT_POP_EN = 0 to drive it manually over beta, but nothing changes.

                • The calculated CRC is transmitted when beta use_crc (CYU3GPIF_BETA_USE_CRC) is set and alpha update_dout (CYU3GPIF_ALPHA_UPD_DOUT) is asserted.

                As I understand I should receive CRC value from FX3 over data bus. For a test I tried to read mailbox register, set use_crc beta with update_dout alpha and expected to receive checksum, but it doesn't happen.

                • The incoming CRC is sampled when beta use_crc (CYU3GPIF_BETA_USE_CRC) is set and beta wq_push (CYU3GPIF_BETA_PUSH_WQ) is asserted.

                I also tried to send CRC to get GPIF_CRC_CONFIG.CRC_RECEIVED changed, but it remains zero.

                 

                P.S. GPIF is quite complex, could you please send some more information about it? Maybe some waveforms or even HDL simulation? Any additional information will help.

                 

                Best regards

                • 5. Re: FX3 GPIF CRC engine (again)
                  inanity407_2949331

                  Hi

                   

                  Unfortunately I really need to get this CRC work.

                  Will be grateful for the help.

                   

                  Thanks in advance

                  • 6. Re: FX3 GPIF CRC engine (again)
                    KeerthyV_76

                    Hi,

                     

                    Can you please provide the complete state machine and timing diagram (by probing the lines using scope)?

                    We will analyze the same and will provide you an update.

                     

                    Regards,

                    Keerthy

                    • 7. Re: FX3 GPIF CRC engine (again)
                      inanity407_2949331

                      Hi,

                       

                      Sorry for delay, now I'm ready for real time communication.

                      I have developed an extremely simple test project for different experiments.

                       

                      There are several things, that are not clear for me. But for simplicity let me ask more concrete questions to solve this problem step by step. So we have a simple project (no USB logic). In current project I configure AP to receive 32 bytes over mailbox and send 32 bytes from CPU to AP over manual dma. At this step I want to see expected CRC16 of sent 32 data bytes in GPIF_CRC_DATA.CRC_VALUE (0xE0014128) register.

                       

                      Here is GPIF state machine configuration with my patches for CRC calculation:

                      - GPIF_CRC_DATA.CRC_VALUE register is initialized in GPIF state INIT_CRC by pulling CYU3GPIF_BETA_INIT_CRC.

                      - CYU3GPIF_BETA_CALC_CRC is pulled in states ADDR and READ for calculation of outgoing data.

                      test_crc_init+calc.png

                       

                      After successful transfer I can see GPIF_CRC_DATA.CRC_VALUE = 0xFB97.

                       

                      crc_value.png

                       

                      Actually see: CRC-16/CCITT-FALSE (0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007) = 0xFB97

                      Expected to see: CRC-16/CCITT-FALSE (0xC0DE1000, 0xC0DE1001, 0xC0DE1002, 0xC0DE1003, 0xC0DE1004, 0xC0DE1005, 0xC0DE1006, 0xC0DE1007) = 0x5C66

                       

                      Test project and .VCD waveforms are attached.

                       

                      QUESTION: I run GPIF in 32-bit mode, but that CRC16 does not use higher 16 bits of data bus during calculation. How to make it work in 32-bit mode, not 16-bit?

                       

                       

                      Regards

                      • 8. Re: FX3 GPIF CRC engine (again)
                        inanity407_2949331

                        Hi

                         

                        I'm running out of ideas how to make it work properly. Really need support.

                         

                        Thanks in advance

                        • 9. Re: FX3 GPIF CRC engine (again)
                          inanity407_2949331

                          Hi

                           

                          Still need support.

                           

                          Regards

                          • 11. Re: FX3 GPIF CRC engine (again)
                            inanity407_2949331

                            Hi

                             

                            Sorry, is there any change to get support for my case? Is this forum the only way to get support from Cypress?

                            I'm sure one need ~20min to find out the way this CRC works having all development sources.

                             

                            Thanks

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