Programmable frequency divider for external signal

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RAP_2366941
Level 1
Level 1

I have external signal in the range of 5 to 10 Mhz, I need to divide(Programmable max 7-bit) it and make it available on port.

I tried using Frequency Divider but it does not provide programmable option.

I', using CY8C4245PVI.

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5 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Use 7-bit down counter, it is programmable.

/odissey1

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Thanx Sir

But unfortunately I have consumed all 4 UDBs available. And I have also

used one 7-bit Down counter.

"Unable to pack the design into 4 UDBs."

Ravi

On Mon, 21 Jan 2019 at 15:18, user_342122993 <community-manager@cypress.com>

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ravipulsundar,

So actual problem is lack of h/w resources. The Count7 consumes only one Control register. How many CRegs are already used? If permitted, post your project for review, maybe there are ways to optimize it.

/odissey1

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Following are my resource utilization table

Resource Type : Used : Free : Max : % Used

============================================================

Digital Clocks : 1 : 3 : 4 : 25.00 %

Interrupts : 5 : 27 : 32 : 15.63 %

IO : 15 : 9 : 24 : 62.50 %

Segment LCD : 0 : 1 : 1 : 0.00 %

CapSense : 0 : 1 : 1 : 0.00 %

Die Temp : 0 : 1 : 1 : 0.00 %

Serial Communication (SCB) : 1 : 1 : 2 : 50.00 %

Timer/Counter/PWM : 2 : 2 : 4 : 50.00 %

UDB : : : :

Macrocells : 22 : 10 : 32 : 68.75 %

Unique P-terms : 37 : 27 : 64 : 57.81 %

Total P-terms : 39 : : :

Datapath Cells : 4 : 0 : 4 : 100.00 %

Status Cells : 3 : 1 : 4 : 75.00 %

Sync Cells (x5) : 2 : : :

Routed Count7 Load/Enable : 1 : : :

Control Cells : 3 : 1 : 4 : 75.00 %

Control Registers : 1 : : :

Count7 Cells : 2 : : :

Comparator/Opamp : 0 : 1 : 1 : 0.00 %

LP Comparator : 0 : 2 : 2 : 0.00 %

SAR ADC : 0 : 1 : 1 : 0.00 %

DAC : : : :

7-bit IDAC : 0 : 1 : 1 : 0.00 %

8-bit IDAC : 0 : 1 : 1 : 0.00 %

============================================================

When I'm trying to use Count7, I get error of *"Unable to pack the design

into 4 UDBs"*

Plz suggest the solution

On Tue, 22 Jan 2019 at 19:22, user_342122993 <community-manager@cypress.com>

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raviphulsundar,

If permitted, post the project for review: (1). Build->Clean, (2) File->Create workspace bundle->Minimal, (3) in created archive file delete folder "Generated_source" to save space.

Maybe there are some other ways to save resources.

/odissey1

                                                                 4.                                 Re: Programmable frequency divider for external signal                                                    

                      

     raviphulsundar_2366941     Level 2                       

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