2 Replies Latest reply on Feb 6, 2019 5:22 AM by BragadeeshV_41

    CapSense interferes with writing to shift register


      I am using a shift register to send out a bit stream (about 2000 bits at 3.3MHZ) which has very tight timing requirements.

      The code to write to the shift register is executed inside a critical section.


      Without CapSense, everything works fine.


      With CapSense, timing problems arise. I was supposing that the interrupt of the CapSense leads to these problems, but other means to disable interrupts like CyGlobalIntDisable have no effect either. I am running out of ideas to solve this problem. Any ideas?