- Please let us know if there is loss of data that is being sent from FX3 or are you seeing 'Failures' on the Streamer application.
- What is the DMA buffer size and count that you are using in the firmware?
- Are you using the FLAGB as the DMA_Ready flag or DMA_Watermark flag. Please confirm if you are following any of the Cypress application note examples.
There is not loss of data that is being sent from FX3, and I did not see 'Failures' on the Streamer application.
the DMA buffer size and count set below:
#define BURST_LEN 8
#define DMA_BUF_SIZE (16)
/* Slave FIFO P_2_U channel buffer count */
#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (8)
/* Slave FIFO U_2_P channel buffer count */
#define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (4)
is there any problem about up set?
I do use "FLAGA" and "FLAGB" signal , and when FLAGB=1, I pull down the "slwr" and send data to FX3 from my FIFO(size:16384x32bit) in FPGA.
The problem is that FLAGA and FLAGB sometimes will pull down sometime(eg: about 10us or other) ,so my FIFO will full and loss some data,.
I have seen AN65974, but I can not understand DMA_Watermark , I did not modify any DMA_Watermark in the firmware.
1. DMA buffer settings are fine.
2. FLAGA is defined as Active Low in the AN65974. This means that whenever FLAGA is LOW, the FX3 is ready to take data from the external interface. So, the SLWR must be pulled LOW when the FLAGA is LOW.
3. FLAGB is a DMA watermark flag. This indicates that the buffer is about to be full in another x clock cycles (where x depends on the GPIF II bus width and watermark value. Please refer to section 8.2, 8.3 of the AN65974 application note for details on the Watermark flag implementation). So, when FLAGB is pulled HIGH, it indicates that the DMA buffer is about to be full in another x clock cycles and the FPGA must drive the SLWR HIGH after x clock cycles.