3 Replies Latest reply on Feb 6, 2019 9:48 PM by SrinathS_16

    I'm using CYUSB3014. I need to upload data from FPGA via CYUSB3014 to PC.

    yoyac_3933486

      Hello,

           I'm using CYUSB3014. I need to upload data from FPGA via CYUSB3014 to PC. I use slave_fifo mode and I use FPGA test procedure 'fpga_slavefifo2b_verilog_ok'  from cypress, I use the "Streamer" software from cypress, and the Packets per Xfer is 8, the packet length is 8192 bytes, then I see the Transfer Rate is about 120MB/s. But, when I upload the data,which speed is constant 80MB/s. When upload some packets(8*8192bytes) , then I find the sigal "flagb" will keep 0 for some time ,which will result in missing some packetscan not upload. I want to know Why did this happen?  is it in sometimes the speed is very low? if I should add a big fifo or DDR to buffer my data. thanks!

       

        • 1. Re: I'm using CYUSB3014. I need to upload data from FPGA via CYUSB3014 to PC.
          SrinathS_16

          Hello,

           

          - Please let us know if there is loss of data that is being sent from FX3 or are you seeing 'Failures' on the Streamer application.

          - What is the DMA buffer size and count that you are using in the firmware?

          - Are you using the FLAGB as the DMA_Ready flag or DMA_Watermark flag. Please confirm if you are following any of the Cypress application note examples.

           

          Best regards,

          Srinath S

          • 2. Re: I'm using CYUSB3014. I need to upload data from FPGA via CYUSB3014 to PC.
            yoyac_3933486

            1.

                 There is not loss of data that is being sent from FX3, and I did not see 'Failures' on the Streamer application.

            the DMA buffer size and count set below:

            #ifdef STREAM_IN_OUT

            #define BURST_LEN 8

            #define DMA_BUF_SIZE (16)

            /* Slave FIFO P_2_U channel buffer count */

            #define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U      (8)

            /* Slave FIFO U_2_P channel buffer count */

            #define CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P  (4)

            #endif

            is there any problem about up set?

             

            2.

                 I do use "FLAGA" and "FLAGB" signal , and when FLAGB=1,  I pull down the "slwr" and send data to FX3 from my FIFO(size:16384x32bit)  in FPGA.

            The problem is that  FLAGA and FLAGB sometimes will pull down sometime(eg: about 10us or other) ,so  my FIFO will full and loss some data,.

            3.

               I have seen AN65974, but I  can not understand  DMA_Watermark , I did not modify any  DMA_Watermark in the firmware.

                        ---thanks!@srnt

             

            • 3. Re: I'm using CYUSB3014. I need to upload data from FPGA via CYUSB3014 to PC.
              SrinathS_16

              Hello,

               

              1. DMA buffer settings are fine.

              2. FLAGA is defined as Active Low in the AN65974. This means that whenever FLAGA is LOW, the FX3 is ready to take data from the external interface. So, the SLWR must be pulled LOW when the FLAGA is LOW.

              3. FLAGB is a DMA watermark flag. This indicates that the buffer is about to be full in another x clock cycles (where x depends on the GPIF II bus width and watermark value. Please refer to section 8.2, 8.3 of the AN65974 application note for details on the Watermark flag implementation). So, when FLAGB is pulled HIGH, it indicates that the DMA buffer is about to be full in another x clock cycles and the FPGA must drive the SLWR HIGH after x clock cycles.

               

              Best regards,

              Srinath S