1 Reply Latest reply on Jan 21, 2019 2:17 AM by SudheeshK_26

    S25FL128S VHDL Model Block Statement


      Hi Guys,


      I have downloaded the S25FL128S VHDL model (from http://www.cypress.com/simulation-models), added to my project in Xilinx Vivado and tried to synthesize but got the following error message:"ERROR: [Synth 8-26] block statement with generics or ports not implemented".


      It seems that Vivado can't synthesize the "Main Behavior Block" that has a port and port map inside.

      I have searched everywhere but couldn't find much information about the Block statement and what I am doing wrong.


      For VitalBuf and VitalWireDelay I got the following message: "WARNING: [Synth 8-312] ignoring unsynthesizable construct: non-synthesizable procedure call". In Vivado it also seems that these are not being found for some reason:

      Could you please give some advice on that?


      Thanks in advance,