4 Replies Latest reply on Jan 19, 2019 5:39 PM by BiBi_1928986

    PSOC TCPWM_CNT_TR_CTRL0 4- bit fields


      Can't find Cypress data on the definitions related to the 4-bit fields that are programmed into PSOC4000 register TCPWM_CNT_TR_CTRL0.  Based on Family Arch TRM 001-89309 rev-D, Figure 16-2, there are 5 trigger inputs from GPIO, Level 0 and Level 1.  There must also be a disable setting represented by these 4-bits.  At least 8 definitions in total.


      Where is a table relating the above mentioned inputs along with their corresponding 4-bit code representation?  It's not in the 'register' doc.  It's not in the datasheet.  It's not in the 'architecture' doc.

        • 1. Re: PSOC TCPWM_CNT_TR_CTRL0 4- bit fields

          Yes, register description is not very clear, but this won't affect you use it because the 'pin assignment editor' of Creator provide you only valid pin list(pins marked as TCPWM[x:x].tr_in[x]) for each input terminal when you assign pins.


          Actually pins marked as TCPWM[x:x].tr_in[x] can be assigned to any function of the 5 options.

          • 2. Re: PSOC TCPWM_CNT_TR_CTRL0 4- bit fields

            Hello xzng.

            I'm in agreement with your comment regarding Creator and pin assignments.  However, in my application, I have to Start the Timer using an edge, make a measurement (after Stopping the Timer through s/w), and then reprogram the Timer to start from s/w trigger and time-out as a one-shot.  Creator is great for setting up the registers the first time through.  It's up to my s/w to set up the Timer registers the second time through.  And for that, I need to know the 4-bit field definitions.

            Thanks for your comment.

            • 3. Re: PSOC TCPWM_CNT_TR_CTRL0 4- bit fields



              Use the following bit field positions.

              Level 0 000

              Level 1 001

              0.0 -> 010

              0.1 -> 011

              0.2 -> 100

              0.3 -> 101

              0.4 -> 110


              These information can be found in the cyfitter file that is generated by the Creator.




              • 4. Re: PSOC TCPWM_CNT_TR_CTRL0 4- bit fields

                Thank you Bragadeesh.  That's the information I've been looking for.  It would be an improvement if this information was included in the 4000 Register TRM document.


                The last bit of information that's missing is the 4-bit value to disable those 7 triggers to allow s/w to exclusively Start/Stop the Timer.  I need to, later in my application code, be able to disable those triggers otherwise s/w can not take control of the Start/Stop feature.  I could try using the default values shown in the Register TRM, but that would Start the Timer running when Level 0 is present and that's not what I need.  The later part of my application needs exclusive start/stop control under software control.


                It's also possible I don't fully understand the meaning of Level 0, Level 1, since these are not referencing a GPIO pin and they are not explained in any Cypress documentation.  I only know that s/w can start/stop the Timer using register TCPWM_CMD (bit 24 and bit 16), assuming no other trigger mechanism has been selected.