Could you please share your circuit too ?
What is the impedance of your external RLC circuit? I wonder if the problem you're seeing is that you are exceeding the drive capability of the pin's output when you don't use the PGA.
It possible I don't fully understand your issue. However here goes: The VDAC output is very limited in current drive. so if the issue you're seeing is when you drive the RLC circuit directly with the VDAC output, the lower impedance can cause the higher internal impedance of the VDAC (4K ohms for 1V range and 16K ohms for 4V range) to be significant. However routing the VDAC through an Op-amp or PGA can allow the PSoC Creator to assign certain port pins that allow up to 25mA drive (<200 ohms).
In short: Be careful using VDACs directly to the external world. It can be used when connecting to circuits of high impedance. This means that the out circuit will be lower in bandwidth. If higher drive (and bandwidth) is required, go through an Op-Amp or PGA component for leaving the IC.
I hope this helps.
Could the issue be the fact that the VDAC is an 8-bit DAC?
Both the VDACs and IDACs are limited in current drive. Using these components for more than signal-level analog will be problematic.
Luckily, Cypress provides 4 Opamps in the PSoC5 with 25mA drive if routed to pins P0, P0, P3 and P.
In modern HW design general terms, it's good practice to assume that a CPU current drive is limited to 5mA. Therefore all power dependent circuits should be external to the CPU.
There are at least two primary reasons for this.
- The more current sourced or sunk from CPU pins, the more power dissipation required by the CPU. Since CPUs can operate near 100MHz, there is enough internal power dissipation (PD). Adding I/O into the PD equation brings its challenges.
- When "large" current sourcing or sinking is occurs, there is a voltage drop at VDD or VSS (respectively). This is called supply or ground "bounce". If there are very sensitive analog circuits needing a reliable (no-ripple) VDD or VSS as supplies or references (like an ADC), this could cause some undesirable variation in these circuits. You can't eliminate supply and ground bouncing but you can minimize it. This is why I try to use differential mode inputs for ADCs even if the '-' input is straight to GND. Single-end mode uses internal common grounds as its reference.