1 Reply Latest reply on Jan 14, 2019 8:18 PM by XiaoweiZ_71

    Externally Clocking a PSoC counter at about 2 GHz with CY294x

    rybac_3975291

      I was wondering if Cypress has an inexpensive solution for counting the time interval/difference between two separate pulses with at least couple of nanosecond resolution. The pulses are TTL, 50 nanosecond wide . Any ideas? Can you run a PSoC counter, externally clocking it with a with 2 GHz a cypress clock, e.g. CY294x? If so what PSoC chip do your recommend, what timer, and maybe if you could suggest sample schematic. Any suggestions would be much appreciated. Thanks.

        • 1. Re: Externally Clocking a PSoC counter at about 2 GHz with CY294x
          XiaoweiZ_71

          Some PSoC6 parts support UDB resources which include 96 DFF blocks can be used for clock dividing but the limitation is PSoC6 IOs are not designed for such application, the IO input capacitance is pF level (<=5pF) and maximum GPIO input operation frequency is 100MHz, seems it is not possible to route a GHz signal into PSoC6 IO directly.

           

          If you can divide the GHz signal to a <100MHz signal externally, then we can use internal UDB resource to divide the signal into a HZ level signal finally and do the measure use a Timer/Counter.