3 Replies Latest reply on Jan 27, 2019 10:23 PM by scotth_21

    For S25FL128S, some questions about SDR AC Characteristics.



      I am using the flash chip of CYPRESS,S25FL128SAGNFI000, but I have some questions that I don't understand  about the SDR AC Characteristics.


      Question 1, At the 5.4 SDR AC Characteristics of the datasheet, Note 23/24/25, such as 23: Full VCC range (2.7 - 3.6V) and CL = 30 pF,

      what't the meaning of the parameter "CL"?


      Question 2, about the parameter of tv(Clock Low to Output Valid).

      The datasheet says that the tv max value is 8.0ns when Note 23 happens.

      but when the tv=8.0ns happens, about the SPI Single Bit Output Timing like Figure 32, it will happens like this:


      Because the tv=8ns, so the time interval between CLK falling edge and rising edge must be greater than 8ns, so one period of CLK must be greater than 16ns.

      So the CLK wil be less than 62.5MHz.

      But for the single commands such as RDSR1, the SCK Clock Frequency can be 133MHz max.

      So here is the question, according to the tv, the SCK frequency of single commands must be less than 62.5MHz, But according to the datasheet, the SCK frequency can be max 133MHz. I think there is contradictions between the two frequency.


      Could help me to explain why this phenomenon happens?


      Thank you so much and looking forward to your reply.

        • 1. Re: For S25FL128S, some questions about SDR AC Characteristics.



          "CL" means load capacitance. Please see more details under AC test conditions on page 28 of the datasheet.


          Maximum value for tV spec is given in datasheet. You will be able to read output data before 8ns from our device at 133MHz. I will discus this query internally and provide more details as soon as possible.

          Thanks and Regards,


          • 2. Re: For S25FL128S, some questions about SDR AC Characteristics.


            Thank you so much for your help.


            About the Question2, Is there any progress?


            About the question1, I understood that, thank you very much.

            • 3. Re: For S25FL128S, some questions about SDR AC Characteristics.

              Hi Xiaowei,


              Thanks again for your question :-)

              It depends on how the MCU’s SPI controller is designed. But in many cases, an SPI controller which supports relatively high clock frequency latches out-coming data on the following red circle period (it should be described on the MCU specification). Briefly, the red circle (data setup time + data hold time) is saying the data on SO will be read in this time period at MCU point of view. Therefore. flash memory should load the read data on SO bus before data setup time is reaching. But there is one more thing - if the MCU specification says it requires a longer data setup time, then the valid window from the falling edge ahead to the starting data setup time will be shorter. That may limit to use higher clock frequency. For example, from the following case, if the MCU requires 3ns data setup time, then the data should be on SO bus within 13ns (16ns - 3ns) from a falling edge ahead. This may limit using max clock frequency.

              Best regards,