"CL" means load capacitance. Please see more details under AC test conditions on page 28 of the datasheet.
Maximum value for tV spec is given in datasheet. You will be able to read output data before 8ns from our device at 133MHz. I will discus this query internally and provide more details as soon as possible.
Thanks and Regards,
Thank you so much for your help.
About the Question2, Is there any progress?
About the question1, I understood that, thank you very much.
Thanks again for your question :-)
It depends on how the MCU’s SPI controller is designed. But in many cases, an SPI controller which supports relatively high clock frequency latches out-coming data on the following red circle period (it should be described on the MCU specification). Briefly, the red circle (data setup time + data hold time) is saying the data on SO will be read in this time period at MCU point of view. Therefore. flash memory should load the read data on SO bus before data setup time is reaching. But there is one more thing - if the MCU specification says it requires a longer data setup time, then the valid window from the falling edge ahead to the starting data setup time will be shorter. That may limit to use higher clock frequency. For example, from the following case, if the MCU requires 3ns data setup time, then the data should be on SO bus within 13ns (16ns - 3ns) from a falling edge ahead. This may limit using max clock frequency.