1 Reply Latest reply on Jan 5, 2019 3:41 AM by KandlaguntaR_36

    How to configure CX3 MIPI receiver configuration for streaming RAW10 4096x3072 @ 10 fps ?


      I am using CX3 with OV12895 image sensor. I am able to capture RAW10 video stream of 4096x3072@ 5 FPS using CX3 MIPI receiver configuration as per CX3_conf_4096x3072_5FPS_working.png




      Now, I want to capture RAW10 video stream of 4096x3072@ 10 FPS. I have following questions.


      1) CX3_TRM mentions that "CX3 is ideally suited for high-definition or high-speed image capturing applications and is capable of streaming uncompressed video up to 1080p at 30 fps or 720p at 60 fps" but it does not mention about 4096x3072 resolution. Is CX3 capable of supporting video stream of 4096x3072@ 10 FPS ?


      2) Assuming that there are no limitations on CX3 for 4096x3072@ 10 FPS, I tried to use CX3 MIPI receiver configuration as per CX3_conf_4096x3072_10FPS_not-working.png, but I have no success. Can you please let me know if MIPI receiver configuration in CX3_conf_4096x3072_10FPS_not-working.png is correct ?

      To manage PCLK within supported limits of CX3, I used 24bit (instead of 16-bit) Video format output i.e RGB888 (Input format is is still RAW10). I also used CY_U3P_MIPICSI_BUS_24 while calling CyU3PMipicsiGpifLoad(). I assume that GPIF will receive packed data with this settings ( 4 pixel data in 5 bytes). Is this understanding correct?




      3) I expect H-ACtive to be 4096 (same as CX3_conf_4096x3072_5FPS_working.png) but it is 1706.66. Is something wrong? How can I make it greater?


      4) What is the formula for computing timing H-ACtive, H-Total, V-Active, V-Total in MIPI CSI2 Inputs (Timing) ?


      5) What is the formula for computing timing H-ACtive, PHY Time Delay value, H Active, H Blanking in CX3 MIPI Interface configuration ?


      Please help.





      Message was edited by: Tejendra Joshi

        • 1. Re: How to configure CX3 MIPI receiver configuration for streaming RAW10 4096x3072 @ 10 fps ?

          1. Yes, it supports 4096x3072 at 10 fps RAW10. Please refer question 6. in this KBA CX3 Firmware: Frequently Asked Questions - KBA91297



          What is the maximum resolution supported by CX3?


          CX3 can support up to 2.4 Gbps (300 MBps) throughput.


          You should make sure that the throughput does not exceed 2.4 Gbps. The throughput can be determined by the formula given below.


          Image throughput = bits per pixel × (Horizontal resolution + Horizontal blanking) × (Vertical resolution + vertical blanking) × frames per second


          For example, some of the resolution, frame rate, and color formats supported by CX3 are given below:


          Contact Cypress technical support if you have more questions on color format and frame rate support.


          • 1920 × 1080 (FHD) , 30fps,60fps in YUV422 format
          • 1280 × 720p (HD), 60fps, 120fps in YUV422 format
          • 3840 × 2160 (uHD, 4k x 2k), 16fps in YUV422 format, 30fps in JPEG format with MJPEG 6:1 compression
          • 4096 × 2160 (4k native), 30fps in RAW8 format
          • 13MP , 10fps YUV422 format
          • 8MP, 16 fps YUV422 format

          2. Yes, your understanding is correct. Have you configured Phy Time  Delay Value using CyU3PMipicsiSetPhyTimeDelay' API?


          This value is calculated based on THS Prepare and THS Zero provided by you and CSI RX Clock generated by the MIPI Tool. See in right bottom corner of the MIPI Receiver Configuration

          i.e RoundUP { [THS_Prepare + (THS_Zero/2)] / [(1/ (CSI RX Clock*1000)] -1}


          Please probe VSYNC and HSYNC test pins, enable the debug prints then collect the logs. Also check whethere there is any mipierrors using CyU3PMipicsiGetErrors API.


          3. You are receiving 4096 pixel of 10 bits each, but MIPI block is sending 24 bits at 98.4 MHz in 1706.6 us


              4096 x 10 = 1706.6 x 98.4 x 24  -> Hence, 1706.6 us is correct.


          4. Let us calculate the pixel clock for your resolution.


          Pixel Clock = (1/frame rate) / (VTotal X HTotal)  = 6.77 ns ~ 147.8 MHz

                                VTotal = 3072 + 256 ; HTotal = 4096+341


          Minimum CSI clock for the given resolution = The rate at which the data coming from the image sensor / (2 x Number of data lane)


          CSI clock minimum = (HActive (Pixel) x data format (RAW 10))/ (HTotal (Pixel) x PCLK (time)) / (2 x 4 data lane)                        = 170.55 MHz ( Tool shows 410 MHz, which is incorrect, please ignore this)


          The MIPI receiver samples the data on both the edges. Hence, there is 2 in the above formula.


          HTotal (time) = Pixel Clock * (HActive + HBlanking) = 30.02 (us)


          If we operate the CSI clock higher than minimum value, the Hactive time will reduce.


          HActive (time) = = 1/(csi_clk*2*lanes)*data_fmt*H_active_pixels (us) = 12.488 us


          VTotal (time) = 1/10 = 100 (ms)


          VActive (time) = V_active = H_Total(in sec)*(V_active_lines)/1000  (ms)



          H_active (time)      = (1/(output_pixel_clock)) * (H_active_pixels) * (bits_per_pixel/gpif_bus_width)

                                output pixel clock = 98.4 MHz, H_active_pixels = 4096, bites per pixel = 10, gpif_bus_width = 24


          H Blanking (time)  = H_Total(calculated in MIPI CSI-2 inputs, i.e provided in question 4) - H_active time


          It looks like you are using older tool, please upgrade to SDK 1.3.4.

          Here is the screenshot of MIPI tool and configuration. Can you please try with this configuration settings.



          CyU3PMipicsiCfg_t Ex_RAW10_Resolution0 = 


              CY_U3P_CSI_DF_RGB888,  /* CyU3PMipicsiDataFormat_t dataFormat */

              4,                          /* uint8_t numDataLanes */

              2, /* uint8_t pllPrd */

              122, /* uint16_t pllFbd */

              CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */ 

              CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */

              CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */

              0,                 /* uint16_t mClkCtl */

              CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */

              4096,         /* uint16_t hResolution */

              0                         /* uint16_t fifoDelay */



          Phy delay is 11