Thank-you for that information.
I would have thought that Mouser would be selling production chips not engineering samples.
I am quite happy to add some capacitance to the power supply to get rid of noise, however the rise time of the power supply will be much slower that the 50 V/us specified in the data sheet. I will add a 470 uF to the rail and a low ESR cap as well.
Where can I get the latest chips which are properly configured. I have spent A$75 on two chips which have problems and don't want to end up spending another A$75 on two more engineering samples.
I purchase my components mainly from DigeyKey and Mouser.
I will let you know how I get on with adding caps.
Hi Again Shivendra,
I added the cap, and realised when I added it that I hadn't connected the negative of the caps to the ground on the chip.
This fixed the problem.
Thanks for your advice, you have restored my faith in FRAM.
Thank you for the update. Good to hear that setup is working now. Some comments on the VCC rise time specification for the F-RAM.
The VCC rise time spec in the datasheet is 50 us/V (min) which translates to 20kV/s (max). Therefore, as long as the power supply ramps at a rate 20kV/sec or below (<=20kV/sec), it would meet the FRAM requirement. Hence, adding a larger decap will slow down the power supply ramp, therefore would work in favor of F-RAM. I believe this clarifies any further concerns on meeting the power up ramp requirement for the FRAM.