4 Replies Latest reply on Jan 21, 2019 2:20 AM by isnac_4001306 Branched from an earlier discussion.

    Re: Issues with FRAM CY15B104Q-SXI SPI communication

    ShivendraS_56

      Hi Rob,

      The timing diagrams and power up specifications look within device spec. From the shared device picture it looks like you are evaluating our new Excelon family product with inrush current control where the typical ISB is expected <5 uA. So, if you are measuring the ISB (with CS low) 2.4 mA in the standby mode indicates some issue either with the setup or the device itself. The new devices shouldn't measure active current <1 mA in case they are in active mode (CS low) but not accessed. I don's see any issue with the SPI timing, therefore it should work if the setup is correct. Is the device on different PCB than controller? If yes then I would suggest adding more GND connection. I see occasional glitch on the VDD rail and clock, please make sure noise is filtered when accessing the device. Otherwise, any noise on the clock can cause latching the wrong opcode by the device. Try putting additional decap (uf range) on the VDD supply. 

       

      SO is driven only when the FRAM device responds with an output data following a valid opcode cycle.

       

      The top marking shows a date code of 1743, which is the very first engineering samples (**) and some of the fields such as DID were not correctly configured in those parts. I would recommend using the latest Excelon samples or use the 4Mb production device (http://www.cypress.com/part/cy15b104q-sxi )  in case it meets your operating voltage requirement.

       

      http://www.cypress.com/documentation/datasheets/cy15b104qicy15v104qi-excelon-lp-4-mbit-512k-8-serial-spi-f-ram-prelimina…

       

      Please contact your local sales for sample request. In case there is no local support, please let us know our marketing team can help to arrange Excelon samples. You can order the existing production samples online.

       

      Thanks,

      Shivendra Singh

        • 1. Re: Issues with FRAM CY15B104Q-SXI SPI communication
          rogac_3959921

          Hi Shivendra,

           

          Thank-you for that information.

           

          I would have thought that Mouser would be selling production chips not engineering samples.

           

          I am quite happy to add some capacitance to the power supply to get rid of noise, however the rise time of the power supply will be much slower that the 50 V/us specified in the data sheet.  I will add a 470 uF to the rail and a low ESR cap as well.

           

          Where can I get the latest chips which are properly configured.   I have spent A$75 on two chips which have problems and don't want to end up spending another A$75 on two more engineering samples.

           

          I purchase my components mainly from DigeyKey and Mouser.

           

          Please advise.

           

          I will let you know how I get on with adding caps.

           

          Best regards

           

          Rob

          • 2. Re: Issues with FRAM CY15B104Q-SXI SPI communication
            rogac_3959921

            Hi Again Shivendra,

             

            I added the cap, and realised when I added it that I hadn't connected the negative of the caps to the ground on the chip.

             

            This fixed the problem.

             

            Thanks for your advice, you have restored my faith in FRAM.

             

            best regards

             

            Rob

            • 3. Re: Issues with FRAM CY15B104Q-SXI SPI communication
              ShivendraS_56

              Hi Rob,

              Thank you for the update. Good to hear that setup is working now. Some comments on the VCC rise time specification for the F-RAM.

              The VCC rise time spec in the datasheet is 50 us/V (min) which translates to 20kV/s (max). Therefore, as long as the power supply ramps at a rate 20kV/sec or below (<=20kV/sec), it would meet the FRAM requirement. Hence, adding a larger decap will slow down the power supply ramp, therefore would work in favor of F-RAM.  I believe this clarifies any further concerns on meeting the power up ramp requirement for the FRAM.

               

              Best Regards,

              Shivendra

              • 4. Re: Issues with FRAM CY15B104Q-SXI SPI communication
                isnac_4001306

                Hi all,

                Cypress CY15B104Q 4-Mbit Serial SPI F-RAM is a 4-Mbit nonvolatile ferroelectric random access memory (F-RAM) logically organized as 512K×8. F-RAM is nonvolatile and performs reads and writes similar to a RAM with reliable data retention of 151 years. The CY15B104Q eliminates the complexities, overhead, and system-level reliability problems caused by serial flash, EEPROM, and other nonvolatile memories.

                Thanks & regards Isaac Nailor from UK

                essay help provider

                1 of 1 people found this helpful