3 Replies Latest reply on Jan 3, 2019 3:20 AM by abhinavg_21

    GPIF-II JTAG state-machine

    user_609701

      I want to use GPIF-II to interface to a device with a 4-bit parallel bus and a 5-pin JTAG. The device needs to be configured via JTAG first. Is it possible to add a JTAG state-machine into GPIF-II ? Once configured via JTAG I then want to capture date from the 4-bit parallel bus

        • 1. Re: GPIF-II JTAG state-machine
          abhinavg_21

          Hi,

           

          Yes you can implement JTAG in GPIF state machine but we don't have any example for it.

          You can implement both(JTAG & 4 bit parallel data fetching) state machines in same project but with different starting state. You can choose the start state while loading the GPIF SM using CyFx3BootGpifLoad().

          Please note one thing that GPIF II can have minimum of 8 bit parallel bus width.

           

          Thanks & Regards
          Abhinav

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          • 2. Re: GPIF-II JTAG state-machine
            user_609701

            Thanks. Very helpful. Is there a way to import an existing VHDL/VERILOG JTAG statemachine (which I have) in to GPIF II or do I need to use the Cypress UX ?             What is the capacity of GPIF II ?

            • 3. Re: GPIF-II JTAG state-machine
              abhinavg_21

              Hi,

               

              You can't import Verilog SM directly into the GPIF II, you have to design your own SM using GPIF II designer tool.

              You can make use of maximum 256 states in one GPIF project.

              For more info on GPIF designer tool see C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\GPIFII_Designer\ gpif2_designer_userguide.pdf

               

               

               

              Thanks & Regards

              Abhinav