14 Replies Latest reply on Mar 10, 2019 11:14 PM by ThM_3776866

    Multi socket 8 bit GPIF interface

    ThM_3776866

      Hi, all,

      I am working on cypress fx3 project. I am able to read and write data from FPGA to Cypress through 8 bit GPIF interface.

      initially I lost data due to  without flow control , After that I follow UVC_AN75779 source code and PDF I am getting correct data without loss and without considering full/empty flag for flow control. Here they are using Multi socket concept.  This is working fine in Lower frequency.

      But my External device (DEMOD) Running at 56 Mhz. so I am getting loss of data ( bulk data loss) I thing DMA buffer switching time is delayed.

       

      Q1 is any change made in code for higher frequency operation?. (Note Clock is external).

      Q2. how to select the DMA buffer for multi socket operation?.( Note I given 4 buffer count but its taken 8) I don't know how?.

      Q3 is any possibility to increase the buffer switching time?.

       

       

      Thank You.

       

       

      With Best Regards,

      Thrimurthi M

        • 1. Re: Multi socket 8 bit GPIF interface
          SrinathS_16

          Hello Thrimurthi,

           

          The AN75779 example uses the multi-channel DMA operation in which the threads are switched alternatively. Buffer switching involves delays whereas thread switching is smooth and no delays are involved. Please let me know the details of your implementation as to whether you switching buffers or threads.

           

          Please refer to section 4 - Setting up the DMA System of the AN75779 document for details on the threads and sockets.

           

          Best regards,

          Srinath S

          • 2. Re: Multi socket 8 bit GPIF interface
            ThM_3776866

            Yes sir, I am using 2 thread 0 and 1 but thing is when I am running 25Mhz external clock from Demod PC capturing a data correctly in USB, but when I running 56MHz external clock frequency Pc capturing a data from USB is misaligned (means its reading 2nd buffer 1st and reading 1st buffer 2nd from cypress).

            • 3. Re: Multi socket 8 bit GPIF interface
              SrinathS_16

              Hello Thrimurthi,

               

              - Please let me know if your design has got the UART debug functionality.

                ->  If yes, kindly, check if the CyU3PDmaChannelCommitBuffer API is returning CY_U3P_SUCCESS for all the transactions.

                ->  If no, please attach the firmware source for me to review.

               

              Best regards,

              Srinath S

              • 4. Re: Multi socket 8 bit GPIF interface
                ThM_3776866

                Hi Srinath sir,

                 

                I am using Auto channel many to one.

                • 5. Re: Multi socket 8 bit GPIF interface
                  ThM_3776866

                  Hi Srinath sir,

                   

                  I can't find here any attach option for attaching the source code.

                  • 6. Re: Multi socket 8 bit GPIF interface
                    SrinathS_16

                    Hello Thrimurthi,

                     

                    Please use the 'Use advanced editor' option to attach files.

                     

                    Best regards,

                    Srinath S

                    1 of 1 people found this helpful
                    • 7. Re: Multi socket 8 bit GPIF interface
                      ThM_3776866

                      Hi Srinath sir,

                       

                      Please find attachment of Multichannel slave FIFO with I2C interface. I am including GIPF Designer also.

                       

                      Thank You.

                       

                      With Best Regards,

                      Thrimurthi.M

                      • 8. Re: Multi socket 8 bit GPIF interface
                        SrinathS_16

                        Hello Thrimurthi,

                         

                        - From the attached GPIF project and the firmware project, I find that the LD_ADDR_COUNT and LD_DATA_COUNT have been set to 511 and the DMA buffer size has been set to 16kB (1024 * 16 bytes). The LD_ADDR_COUNT and LD_DATA_COUNT are to be loaded with a value such that a buffer is full after the specified value of clocks have been passed. In your case, you are using an 8-bit GPIF II interface which means that one byte of data is transferred every clock cycle. So, for one entire buffer to be full, 16384 clock cycles are required. Hence, the LD_DATA_COUNT and LD_ADDR_COUNT should be loaded with 16383 for proper reception of data.

                        - After making the mentioned modification, if there are still errors, please share the UART logs captured.

                         

                        Best regards,

                        Srinath S

                        • 9. Re: Multi socket 8 bit GPIF interface
                          ThM_3776866

                          Hi Srinath sir,

                           

                          I changed the counter value to 16383 (16Kb -1 )  formula given in image sensor implementation application note. I am getting partial data at USB end point (means loss of data).

                          I attached UART Print also do the needful.ts out UART.PNG

                           

                          1.GPIF ERROR CB_ERROR :26  ( means CYU3P_PIB_ERR_THR1_SCK_INACTIVE)

                          2. GPIF ERROR CB_ERROR :18 ( means CYU3P_PIB_ERR_THR0_SCK_INACTIVE) in CyU3PPibErrorType

                           

                           

                          Thank You .

                           

                           

                          with Best Regards,

                          Thrimurthi.m

                          • 10. Re: Multi socket 8 bit GPIF interface
                            SrinathS_16

                            Hello Thrimurthi,

                             

                            - From your GPIF state machine, I can see that in the state WAIT_TO_FILL_SCK0, the jump is made to PUSH_DATA_SCK0 state or PARTIAL_BUF_IN_SCK0 state depending on the value of TS_VALID pin at that instant which can depend on the frequency of the GPIF clock. This can cause improper writing to the FX3 buffers.

                            - Please let know what is the TS_VALID pin in your design and what is the frequency and time period for which it remains HIGH and LOW.

                             

                            Best regards,

                            Srinath S

                            • 11. Re: Multi socket 8 bit GPIF interface
                              ThM_3776866

                              Hi Srinath sir

                               

                              Now I solved CYU3P_PIB_ERR_THR1_SCK_INACTIVE and CYU3P_PIB_ERR_THR1_SCK_INACTIVE. The working GPIF designer I attached here please let me know the attached  GPIF-2 designer is correct or not.

                               

                              In my source code:

                              MultidmaCfg.size  = TS_DMA_BUF_SIZE; // 16Kb
                              MultidmaCfg.count = CY_FX_FIFOLP_DMA_BUF_COUNT; // 4
                              MultidmaCfg.validSckCount = 2;
                              MultidmaCfg.prodSckId[0] = (CyU3PDmaSocketId_t)CY_FX_PRODUCER_PPORT_SOCKET_0; // CY_U3P_PIB_SOCKET_0
                              MultidmaCfg.prodSckId[1] = (CyU3PDmaSocketId_t)CY_FX_PRODUCER_PPORT_SOCKET_1; // CY_U3P_PIB_SOCKET_1
                              MultidmaCfg.consSckId[0] = (CyU3PDmaSocketId_t)CY_FX_TS_CONSUMER_USB_SOCKET;  // CY_U3P_UIB_SOCKET_CONS_2
                              MultidmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
                              /* Enabling the callback for produce event. */
                              MultidmaCfg.notification = 0;
                              MultidmaCfg.cb = NULL;
                              MultidmaCfg.prodHeader = 0;
                              MultidmaCfg.prodFooter = 0;
                              MultidmaCfg.consHeader = 0;
                              MultidmaCfg.prodAvailCount = 0;

                              apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleSlFifoPtoU,
                                CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE, &MultidmaCfg);
                              if (apiRetStatus != CY_U3P_SUCCESS)
                              {
                                CyU3PDebugPrint (4, "CyU3PDmaMultiChannelCreate failed, Error code = %d\n", apiRetStatus);
                                CyFxAppErrorHandler(apiRetStatus);
                              }


                              /* Flush the Endpoint memory */
                              CyU3PUsbFlushEp(CY_FX_EP_CONSUMER_2);
                              CyU3PDmaMultiChannelReset (&glChHandleSlFifoPtoU);

                              apiRetStatus = CyU3PDmaMultiChannelSetXfer (&glChHandleSlFifoPtoU, CY_FX_FIFOLP_DMA_TX_SIZE, 0);
                              if (apiRetStatus != CY_U3P_SUCCESS)
                              {
                                CyU3PDebugPrint (4, "CyU3PDmaMultiChannelSetXfer Failed, Error code = %d\n", apiRetStatus);
                                CyFxAppErrorHandler(apiRetStatus);
                              }

                               

                               

                              I am testing 32 bit increamemt data from external FPGA device. I am reading data through USB end point 0x82. Now I am using C# PC Application to write data to bin file.

                               

                              Problem:

                              I am getting data without data loss, but data is not in incremental order only allocated buffer size of data is correct after am getting some other incremental data (means DMA buffer Reading is not serial order( buffer 1 to 2 to 3 to 4...) , but its reading random order(its reading buffer 2 after buffer 1 after 3 after 4 like this )). 

                               

                              Q1. How resolve this problem?. is there any configuration for multichannel DMA configuration.

                              Q2. How configure the DMA Descriptor  for P-port and USB port. I attached  the image of FX3 data transfer architecture of image sensor in given in AN75779 Doc.

                               

                              multichanel_DMA.PNG

                              • 12. Re: Multi socket 8 bit GPIF interface
                                ThM_3776866

                                Hi Srinath sir,

                                 

                                1. I my design TS_Valid pin used to identify data is in external device buffer ( this signal is input to cypress from external device) TS_valid goes high only when data is in bus. High and low is depends on data is in external buffer (If TS_Valid=1 external device buffer has data and TS_Valid=0 external device buffer is empty).

                                 

                                2. External clock = 56MHz.

                                 

                                3. High and low Time period of TS_ Valid is not constant.

                                 

                                Thank You

                                 

                                Best Regards,

                                Thrimurthi M

                                • 13. Re: Multi socket 8 bit GPIF interface
                                  ThM_3776866

                                  Hi,

                                   

                                  Sorry in GPIF designer counter value is 16383. (for both data and addr)@

                                  1 of 1 people found this helpful
                                  • 14. Re: Multi socket 8 bit GPIF interface
                                    ThM_3776866

                                    Hi All

                                     

                                    I am getting correct incremental data at every fresh start.

                                    Note:

                                    1. The Receiver should be active before TX (  PC App RX Thread should be active before DEMOD transmitting the incremental data).

                                    2. The Problem in GPIF state machine, if you want stop the RX at middle of data capture you have to stop the GPIF State machine before RX thread stop by using the API "CyU3PGpifDisable (CyFalse);"

                                    3. Again start the data capture at middle of DEMOD Transmission you have to start RX thread in pc app and start GPIF state machine in Cypress by using this API "apiRetStatus = CyU3PGpifSMStart (START_SCK0, ALPHA_START_SCK0);".

                                     

                                    code for  GPIF Start and Stop:

                                    void
                                    CyFXStreamStart()
                                    {
                                    CyU3PReturnStatus_t   apiRetStatus;

                                    /* Place the EP in NAK mode before cleaning up the pipe. */
                                    CyU3PUsbSetEpNak (CY_FX_EP_CONSUMER_2, CyTrue);
                                    CyU3PBusyWait (125);

                                    /* Reset and flush the endpoint pipe. */
                                    CyU3PUsbFlushEp (CY_FX_EP_CONSUMER_2);
                                    CyU3PDmaMultiChannelReset (&glChHandleSlFifoPtoU);

                                    /* Set DMA Channel transfer size, first producer socket */
                                    apiRetStatus = CyU3PDmaMultiChannelSetXfer (&glChHandleSlFifoPtoU, 0, 0);
                                    if (apiRetStatus != CY_U3P_SUCCESS)
                                    {
                                      /* Error handling */
                                      CyU3PDebugPrint (4, "DMA Channel Set Transfer Failed, Error Code = %d\r\n", apiRetStatus);
                                    }

                                    CyU3PUsbSetEpNak (CY_FX_EP_CONSUMER_2, CyFalse);
                                    CyU3PBusyWait (125);
                                      /* Start the state machine. */
                                      apiRetStatus = CyU3PGpifSMStart (START_SCK0, ALPHA_START_SCK0);
                                      if (apiRetStatus != CY_U3P_SUCCESS)
                                      {
                                       CyU3PDebugPrint (4, "CyU3PGpifSMStart failed, Error Code = %d\n",apiRetStatus);
                                      }

                                    GPIFActive = CyTrue;

                                    CyU3PDebugPrint (4, "Application Started\r\n");
                                    }

                                     

                                     

                                     

                                    void
                                    CyFXStreamStop()
                                    {

                                    /* Disable the GPIF state machine. */
                                    CyU3PGpifDisable (CyFalse);

                                    /* Place the EP in NAK mode before cleaning up the pipe. */
                                    CyU3PUsbSetEpNak (CY_FX_EP_CONSUMER_2, CyTrue);
                                    CyU3PBusyWait (125);

                                    /* Reset and flush the endpoint pipe. */
                                    CyU3PDmaMultiChannelReset (&glChHandleSlFifoPtoU);
                                    CyU3PUsbFlushEp (CY_FX_EP_CONSUMER_2);
                                    CyU3PUsbSetEpNak (CY_FX_EP_CONSUMER_2, CyFalse);
                                    CyU3PBusyWait (125);
                                    GPIFActive = CyFalse;
                                    CyU3PDebugPrint (4, "Application Stopped\r\n");
                                    }