- Please let us know if your implementation is based on any of the Cypress provided examples.
- If the FX3 DMA channel is configured for 2 buffers, and the FPGA does not read data from the P-Port, the DMA buffers of FX3 become full and hence will not be able to accept new data until the previous data is read by the P-Port interface. So, the FPGA code has to be written such that it monitors the FX3 flag for the presence of data in the DMA buffers and read the same.
Thank you. my firmware is modified based on cypress slavefifo example.
My further question is where is the setting of the number of buffers in the firmware.
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When using the CyU3PDmaChannelCreate() API, the DMA channel configuration structure pointer is passed as a parameter. The count variable of the CyU3PDmaChannelConfig_t structure determines the number of buffers used for the particular channel. In the slave FIFO example that comes with the AN65974, the below macros determine the buffer counts for the two channels used.
dmaCfg.size = DMA_BUF_SIZE* size;
dmaCfg.count = CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P;
dmaCfg.prodSckId = CY_FX_PRODUCER_USB_SOCKET;
dmaCfg.consSckId = CY_FX_CONSUMER_PPORT_SOCKET;
dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
/* Enabling the callback for produce event. */
dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaCfg.cb = CyFxSlFifoUtoPDmaCallback;
dmaCfg.prodHeader = 0;
dmaCfg.prodFooter = 0;
dmaCfg.consHeader = 0;
dmaCfg.prodAvailCount = 0;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoUtoP,
The problem is perfectly solved. Thank you.