Dear Cypress community,
I spent a few days trying to fix an issue with my SPI DMA and found no solution. I hope you can help me.
I'm trying to read out the ADXL372 FIFO using SPI + TX and RX DMA.
The FIFO watermark interrupt causes the TX and RX DMA to start the transfer (inside the ISR).
The TX DMA transfer works very well but the RX transfer seems to transfer one byte less than configured in the component editor.
I set up the accelerometer to trigger the watermark interrupt at 507 FIFO samples which means
that 169 Sample Sets ( 1 Set = 6 bytes x-y-z-Axis data = 1014 bytes + 1 Byte Opcode ) has to be transferred.
Due to the maximum transfer limit of 256 bytes, I decided to configure the DMA components (RX and TX) to transfer 203 Bytes in one X-Loop and
repeat this 5 times. In the RX DMA component, after each X-Loop the destination address is increased by 203 bytes.
An RX DMA complete interrupt should be triggered after the last X-Loop has been finished.
I have configured a GPIO Pin to go High when the DMA transfer is started and go low when the RX Finish interrupt is triggered.
Im using the PSoC 6 EZ BLE Module (CYBLE-416045-02 43-SMT)
In the attachment you can see
- Pictures of logic analyzer recordings
- Pictures of code segments
- Pictures of the component configurations
- Pictures of debug view
Please let me know if you need more information.
I am very grateful for any helpful response and wish everyone a happy new year.