Customer refer to the SRAM read control by "Figure 15. Read Cycle No. 3" in the datasheet on page 12.
In this access, is it possible to read data correctly from SRAM even when "OE goes to Low before CE goes to Low"?
MCU will act the OE signal to Low about 20ns faster than CS signal to Low in worst case.
MPN : CY7C1061G/GE
There will not be any problem if OE goes LOW before CE. The data will be available tACE time after CE goes LOW.