4 Replies Latest reply on Dec 24, 2018 12:33 AM by ShifangZ_26

    CCG1 superspeed intermittent

    PaHo_3246171

      Hi, Using CCG1 as a client like CY4503.  In my application I find that sometimes the device does not enumerate as superspeed device.  The reason is that the CCG1 does not enable the superspeed mux.  What can cause this?

        • 1. Re: CCG1 superspeed intermittent
          ShifangZ_26

          Hi Paul,

           

          CCG1 client board have U10 PI3DBS12412AZHE responsible for USB3.0 or DisplayPort signal switch. CCG1 will drive CCG1_MUXSEL_2 and CCG1_MUXSEL_4 after CC negotiation confirmed which pin assignment the NB/Type-C host support. You can measure this two signals and review the CC negotiations to confirm. For example, If it is 4 lane DP transmit on the line, the USB shall be USB2.0 on Type-C port.

           

          Best Regards,

          Lisa

          • 2. Re: CCG1 superspeed intermittent
            PaHo_3246171

            Hi Lisa,

             

            Thanks for the response.  On my board I do not have the display port mux, only the superspeed mux.  Also, in my configuration I have set the ‘Display Port Mode Parameters -> Modes supported’ to ‘None’.  I thought this would disable display port mode.  Are my DP Mode Parameters perhaps incorrect?  Screenshot below:

             

             

             

            Thanks,

            Paul

            • 3. Re: CCG1 superspeed intermittent
              PaHo_3246171

              Hi Lisa,

               

              One more thing to comment on.  When the error occurs the CCG_MUXSEL_5 line is left floating high.  This line controls the output enable of the mux which is why the port cannot connect with superspeed.

               

              Thanks,

              Paul

              • 4. Re: CCG1 superspeed intermittent
                ShifangZ_26

                Hi Paul,

                 

                1. PI3DBS12412AZHE and PI3PCIE3242ZLE is controlled by CCG1_MUXSEL_5 and the active level is LOW. If you let CCG1_MUXSEL_5 floating, you shall connect OE pins to GND to enable both chips.

                2. If you want to remove DisplayPort from your project, you can refer below configuration.

                3. USB3.0 enumerate process is not only relates with firmware configuration, also need take care hardware layout. You can use USB trace analysis tool to see what the root cause of enumerate failure.

                 

                Best Regards,

                Lisa