8 Replies Latest reply on Dec 21, 2018 12:24 PM by user_342122993

    Karplus Strong verilog help

    user_200706552

      Hi all

       

      I made simple KS_Osc in veriog but PSOC5 have little resources.

       

      Exist way how to replace registers datapath or sram in verilog ?

       

      Second Karplus component is mcu base.

       

      Is possible make this in DFB ?

       

      Thanks help and info.

       

      Kamil

        • 1. Re: Karplus Strong verilog help
          user_342122993

          Kamil,

          there are no projects attached, please add project files.

          /odissey1

          • 2. Re: Karplus Strong verilog help
            user_200706552

            Attached project to first post.

             

            Working but find way to save resources :-)

            • 3. Re: Karplus Strong verilog help
              user_342122993

              Kamil,

              Oups, indeed, the project is there. Sorry, its Saturday now!

               

              Do you want to increase delay line (say to 100 mem registers)?     r

              eg[6:0] mem0,mem1,mem2,mem3,mem4,mem5,mem6,mem7;

               

              The verilog won't handle that, as it is already consumes 70% of P-terms. I believe in this case PSoC RAM buffer can be used instead of PLD registers.

               

              The essential delay loop code:

                         if(cnt==0) begin mem0 <= tmp; curr <= mem0; end
                          if(cnt==1) begin mem1 <= tmp; curr <= mem1; end
                          if(cnt==2) begin mem2 <= tmp; curr <= mem2; end
                          if(cnt==3) begin mem3 <= tmp; curr <= mem3; end
                          if(cnt==4) begin mem4 <= tmp; curr <= mem4; end
                          if(cnt==5) begin mem5 <= tmp; curr <= mem5; end
                          if(cnt==6) begin mem6 <= tmp; curr <= mem6; end
                          if(cnt==7) begin mem7 <= tmp; curr <= mem7; end
              
                          tmp <= ((last>>1) + (curr>>1));
                          last <= curr;
                          cnt <= cnt + 1;
              

               

              it takes 'curr' from the sequential  'mem_i' cell for calculation of  'tmp' and pushes result back into it (maybe to the next cell - needs research). Since it is sequential circular access to the memory (no random access is required), it is easy to setup a RAM buffer and two DMA channels for sequential write and read from status and control registers connected directly to 'curr' and 'tmp' wires. The DMA will handle it because the sampling clock is rather slow (50kHz). The length of the RAM buffer can be quite large, ~100 should suffice for 50Hz output. The reset of the RAM buffer can be done by CPU.

              I have no code, but will look into it, time permits.

              /odissey1

              • 4. Re: Karplus Strong verilog help
                user_200706552

                Hi odissey1

                 

                Thanks for the help of DMA idea.

                 

                I tried to create two DMA channels but I do not understand how to properly route them to SRAM.

                 

                I submit the concept of the project

                 

                Kamil

                • 5. Re: Karplus Strong verilog help
                  user_342122993

                  Kamil,

                  I will look into it on holidays, quite busy now as the year ends.

                  /odissey1

                  • 6. Re: Karplus Strong verilog help
                    user_342122993

                    Kamil,

                    Attached is a basic demo showing sequential RAM access from Verilog.  DMA1 feeds data from RAM buffer to Control Register, the value is modified by Verilog, passed to Status register, and feed back to same location in RAM by DMA2. Then DMA1 switches to next position in RAM. To see the difference, observe analog output on the scope with and without DMA2 enabled. The RAM buffer and DMA configuration can be moved into component API, but for simplicity it is left here as-is.

                    /odissey1

                     

                    DMA_Verilog_01a.png

                    DMA_Verilog_01b.png

                    • 7. Re: Karplus Strong verilog help
                      user_200706552

                      Hi odissey1

                       

                      Thank you so much for the demonstration. Everything works perfectly. It's going to be funny for my other projects.

                       

                      Thank you once again.

                       

                      Kamil

                      • 8. Re: Karplus Strong verilog help
                        user_342122993

                        Kamil,

                        If permitted, please show results on YouTube (Vimeo etc.), it would be interesting to see how PSoC handles Karplus-Strong.

                        /odissey1