4 Replies Latest reply on Jan 3, 2019 6:19 AM by chloc_1378511

    UDB Fifo Problem

      Hi,

      I'm having a problem on a CY8CKIT-049-42XX with the UDB FIFO's.

       

      I have core code that writes into the F0 FIFO (checking before that the FIFO is not full). There is verilog code that has a DP that reads the F0 value into A0 when the FIFO_EMPTY flag is low.

      I initialise the FIFO by writing  0x03, then 0x00 to the AUX Ctrl register for that DP, and following this the flags to the bus and the block indicate that the FIFO is empty.

       

      However, when I write a sequence of bytes into F0 and examine A0 after each write, it is clear that the FIFO still contains data immediately after initialisation that is read out before the data that I have written in.

       

      That is to say, the AUX_REG writes appear to clear the external full/empty flags, but the internal FIFO read/write pointers do not appear to be reset correctly.

       

      Typically I seem to read out 3 "other" values before I see the values that I am writing in.

       

      I appear to see the problem both on UDB00 and UDB03 (I haven't tried the other two).

       

      Any thoughts on the problem?

       

      Regards

      Ziggles

        • 1. Re: UDB Fifo Problem
          DheerajK_81

          Can you please attach your project so that we can look at the code and other settings? Go to Project > Archive >  Minimal and then share the resultant zip file.

           

          Regards,

          Dheeraj

          • 2. Re: UDB Fifo Problem

            Hi Dheeraj,

             

            Attached is a zip of the source files. I hope this is sufficient. The only change in environment settings is the compile optimization so that the  temp variable is not optimized out.

             

            I have tried the problem with PSoC Creator 4.1 and 4.2, and I have tried it on two CY8CKIT-049-42XX boards which are not from the same batch. So I'm pretty convinced that it is something that I am doing wrong. Probably something very simple that I just can't see.

             

            The verilog code simply waits for the internal FIFO0_EMPTY flag to go not empty then commands the DP to read the value into A0.

             

            If you get a chance to look at it, my sincere thanks in advance.

             

            Regards

            Ziggles

            • 3. Re: UDB Fifo Problem
              DheerajK_81

              Hello Ziggles,

               

              Can you attach your entire project? I would like to make changes and test. Please right click on the project > "Archive Workspace/ Project" > Minimal and then share the zip file.

               

              Regards,

              Dheeraj

              • 4. Re: UDB Fifo Problem

                Hi Dheeraj,

                 

                Thanks for taking a look. I'm only able to post the source files, I'm afraid.

                 

                I've tried to minimize the problem to the very basics so that the project would be very simple to re-create, but fully understand if you are unable to look into it any deeper.

                 

                I will try and revisit the problem in the next few weeks to see if I can determine any other information. If I find anything else, I will post the information for the wider community.

                 

                Kind regards

                Ziggles