7 Replies Latest reply on Dec 25, 2018 3:05 AM by TakahiroK_16

    grbage data read from Hyperam

    gapac_3691236

      Dear Support team ,

       

      Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU

       

       

      We have successfully integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI  MCU  and able to read & write  data .

       

      but for some frequency setting we are getting garbage data from HyperRAM for first two bytes .

       

      please refer attached document having details of 3 test case  ( case no 3 having issue of first two bytes garbage )

       

       

      Thanks,

      Gaurav

       

        • 1. Re: grbage data read from Hyperam
          TakahiroK_16

          Hi Gaurav,

           

          In your test case #3, I see the latency cycles is 9. Do you change the configuration register 0 in HyperRAM as well as the host controller?

          The default latency cycles in the HyperRAM is 6. If you use 9 cycles, you need to change CR0[7:4].

           

          Thanks,

          Takahiro

          • 2. Re: grbage data read from Hyperam
            gapac_3691236

            Dear Takahiro ,

             

            Please refer following reply :

             

             

             

            Do you change the configuration register 0 in HyperRAM as well as the host controller? – No we haven’t change setting in CR0. Also in CR0[7:4] possible values are only 3 ,4,5,6 all other values are reserved .

             

             

             

            In our host controller we also changed to default value 6 but same error for 32Mhz clock & working for 24MHz clock .

             

             

             

            Note that this error occurs  only for first 2 bytes . Important observation :

             

            1.      Here data is not garbage instead two garbage data added to original data . meaning that original data shifted by two bytes .

             

            2.      When data written in two steps 252 & 252 bytes from 0 address & read from 0 address then only first two bytes gets garbage value & received 504 bytes after that.

             

            3.      When data written in two steps 252 & 252 bytes & also read in two steps than only first two bytes of first read step gets additional two garbage bytes .

             

             

             

             

             

             

             

             

             

            Thanks & Regards,

             

            Gaurav Patni

            • 3. Re: grbage data read from Hyperam
              TakahiroK_16

              Hi Gaurav,

               

              Sorry, I missed that the 9 cycles is not a possible setting in CR0.

              I think it's better to check what exactly the HyperRAM outputs by using logic analyzer or scope waveform.

               

              Thanks,

              Takahiro

              • 4. Re: grbage data read from Hyperam
                gapac_3691236

                Dear Takahiro ,

                 

                We don't have logic analyzer but can take waveform for 4 channel simultaneously .

                 

                we found very interesting observation , two byte garbage data added to original data during write cycle only when we change/initialize address pointer variable address .

                i.e. when we assign any address to pointer variable . if we don't reassign address then no issue of garbage data .

                 

                we have also tried adding slight delay after address variable initialize but same result for 32Mhz .

                 

                Note : same code is working fine with 24MHz .

                 

                Please suggest why this behavior ?

                 

                refer attached code main body .

                 

                ---------------------------------------------------- Code -------------------------------------------------

                 

                 

                 

                while(1)

                    {

                        /*

                        unsigned char  TxBuffer_3[10] = "kkkkkkkkkk";

                        unsigned char  TxBuffer_2[10] = "bbbbbbbbbb";

                        unsigned char  TxBuffer_1[10] = "cccccccccc";

                        unsigned char  TxBuffer_0[10] = "dddddddddd";

                        */

                       

                       

                //------------------------------------- Write sequentially ----------------------------------------------------

                       

                       

                        // Initially setting the base address to RAM address pointer variable

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE);

                        for (int delay = 0; delay < 10000000; delay++);

                       

                        // Write in (OCTOSPI1_BASE) address to (OCTOSPI1_BASE + 10)

                        for (index = 0; index < 10; index++)

                        {

                            *mem_addr = TxBuffer_0[index]; // getting 2 garbage data if we read this data

                            mem_addr++;

                        }

                       

                        // Write in (OCTOSPI1_BASE + 10) address to (OCTOSPI1_BASE + 20)

                        for (index = 0; index < 10; index++)

                        {

                            *mem_addr = TxBuffer_1[index]; // Not getting garbage data if we read this data as 'mem_addr' is not initialize.

                            mem_addr++;

                        }

                       

                        // Write in (OCTOSPI1_BASE + 50) address to (OCTOSPI1_BASE + 60)

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE + 50);

                        for (int delay = 0; delay < 10000000; delay++);

                        for (index = 0; index < 10; index++)

                        {

                            *mem_addr = TxBuffer_2[index];  // getting 2 garbage data if we read this data as 'mem_addr' is initialize to OCTOSPI1_BASE + 50

                            mem_addr++;

                        }

                       

                        // Write in (OCTOSPI1_BASE + 100) address to (OCTOSPI1_BASE + 110)

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE + 100);

                        for (int delay = 0; delay < 10000000; delay++);

                        for (index = 0; index < 10; index++)

                        {

                            *mem_addr = TxBuffer_3[index]; // getting 2 garbage data if we read this data as 'mem_addr' is initialize to OCTOSPI1_BASE + 100

                            mem_addr++;

                        }

                 

                //------------------------------------- Read sequentially ----------------------------------------------------

                        // Read from (OCTOSPI1_BASE) address to (OCTOSPI1_BASE + 10 + 2) 2 is added to cover the initial two byte error

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE);

                //        for (int delay = 0; delay < 10000000; delay++);

                        for (index = 0; index < 12; index++)

                        {

                            RxBuffer_0[index] = *mem_addr;  // getting 2 garbage data + original 10 bytes

                            mem_addr++;

                        }

                        // Getting 'RxBuffer_0' as "\210\210dddddddddd"

                 

                        // Reading immediate next 10 bytes

                        for (index = 0; index < 10; index++)

                        {

                            RxBuffer_1[index] = *mem_addr; // not getting garbage data received original 10 bytes

                            mem_addr++;

                        }

                        // Getting 'RxBuffer_1' as "cccccccccc"

                 

                        // Read from (OCTOSPI1_BASE + 50) address to (OCTOSPI1_BASE + 60 + 2) 2 is added to cover the initial two byte error

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE + 50);

                //        for (int delay = 0; delay < 10000000; delay++);

                        for (index = 0; index < 12; index++)

                        {

                            RxBuffer_2[index] = *mem_addr; // getting 2 garbage data + original 10 bytes

                            mem_addr++;

                        }

                        // Getting 'RxBuffer_2' as "embbbbbbbbbb" which is shifted by two byte error

                 

                        // Read from (OCTOSPI1_BASE + 100) address to (OCTOSPI1_BASE + 100 + 2) 2 is added to cover the initial two byte error

                        mem_addr = (__IO uint8_t *)(OCTOSPI1_BASE + 100);

                //        for (int delay = 0; delay < 10000000; delay++);

                        for (index = 0; index < 12; index++)

                        {

                            RxBuffer_3[index] = *mem_addr;  // not getting garbage data received original 10 bytes

                            mem_addr++;

                        }

                        // Getting 'RxBuffer_3' as "\210\210kkkkkkkkkk" which is shifted by two byte error

                 

                 

                    }

                • 5. Re: grbage data read from Hyperam
                  gapac_3691236

                  Dear Takahiro ,

                   

                  waiting for your reply...

                   

                  if you are engage in other activity please let us know different experiments / settings for this so that you can troubleshoot easily based on results .

                   

                  Thanks,

                  Gaurav

                  • 6. Re: grbage data read from Hyperam
                    gapac_3691236

                    Dear Takahiro ,

                     

                    waiting for your reply...

                     

                    Thanks,

                    Gaurav

                    • 7. Re: grbage data read from Hyperam
                      TakahiroK_16

                      Hi Gaurav,

                       

                      Sorry my reply is late.

                       

                      Since the HyperRAM is working in Case 1 (36.67 MHz) the fundamentals like HW connection and the HyperRAM itself should be OK. The issue happens when you change the host controller configuration so this more likely a host controller side issue and this seems not my area...

                       

                      I would recommend you to contact STM about this. Personally, I feel strange that you are using same clock frequency for both system and OSPI. In general, the system clock should be higher than peripheral clock.

                       

                      Thanks,

                      Takahiro