3 Replies Latest reply on Jan 3, 2019 3:59 AM by abhinavg_21

    Slave FIFO Read Sequence in Fx3

    ThM_3776866

      Hi All,

      I'm working on Fx3 cypress GPIF Interface. I need to send the data from host to external device through a GPIF interface. I am using DMA_Ready_Flag for Data valid signal to External device and Read signal is from External device to cypress.

      The timing diagram of Slave FIFO Read is given bellow.

      Read_Timming.PNG

      Q1 why data is sampled after 2nd clock cycle of Flag and read signal is assert?.

       

      Please do the needful.

      Thank you

      With Beast Regards,

      Thrimurthi M