Yes, there is a difference in using SPI Master functionality provided by SPI block of FX3/CX3/FX3S (default functionality) and SPI Master functionality implemented through Bit-banging (GPIOs).
In default SPI functionality, you can operate the SPI up to 33 MHz (mentioned in the datasheet).
But in case of Big-banging, you will get in the order of ~ 500 kHz.
We have two example firmware for default SPI Master
- SPI DMA Mode: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspidmamode
- SPI Register Mode: C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspiregmode
One example firmware for Bit-banging implementation.
C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\serialif_examples\cyfxusbspigpiomode
The regular SPI clock frequency can be configured using CyU3PSpiSetConfig() function.
SPI-clock calculation: The maximum SPI clock supported is 33MHz and the minimum is 10KHz. The SPI block needs to be clocked at 2X the interface bit rate. The clock for the SPI block is derived from the system clock through a frequency divider. As the hardware only supports integer and half dividers for the frequency, the firmware uses the closest approximation to the desired bit rate.