Power draw during low power states attributed to GPIO pin configuration

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GrCa_1363456
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How much additional power draw during low power states can be attributed to each specific GPIO pin configuration? I.E. What is the lowest power GPIO pin configuration for a PSoC 5?

To achieve the lowest possible sleep power with a PSoC 5, will setting active and unused GPIO pins to a particular configuration minimize the power draw?

There's an assumption that leaving unused GPIO pins in their default configuration will produce the lowest power configuration. If anyone has found that not to be true in general or for specific pins, that information would be helpful.

Greg

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GeonaP_26
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Please configure unused pins to Analog Hi-Z to reduce power consumption. Please refer to section: GPIOs in PSoC Low-Power Mode of Low-Power Modes and Power Reduction Techniques for more details.

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GeonaP_26
Moderator
Moderator
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250 solutions authored 100 solutions authored 50 solutions authored

Please configure unused pins to Analog Hi-Z to reduce power consumption. Please refer to section: GPIOs in PSoC Low-Power Mode of Low-Power Modes and Power Reduction Techniques for more details.

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