1 Reply Latest reply on Dec 9, 2018 9:20 PM by GeonaP_26

    Power draw during low power states attributed to GPIO pin configuration


      How much additional power draw during low power states can be attributed to each specific GPIO pin configuration? I.E. What is the lowest power GPIO pin configuration for a PSoC 5?

      To achieve the lowest possible sleep power with a PSoC 5, will setting active and unused GPIO pins to a particular configuration minimize the power draw?

      There's an assumption that leaving unused GPIO pins in their default configuration will produce the lowest power configuration. If anyone has found that not to be true in general or for specific pins, that information would be helpful.