Which is definitive: the VHDL model file or the data sheet for the S29CL032J?

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DaBa_3845446
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A close study of the VHDL model file provided for the S29CL032J device has discrepancies with the stated behaviour in the device's datasheet. Is the VHDL model more definite than the datasheet, or is the datasheet more definitive? A case in point is the use of DQ5 for reporting program and erase errors, which is missing from the VHDL code (DQ5 is always zero). This might simply be behaviour that the VHDL model was not intended to cover, but if this is the case then there is no clear statement to that effect.  There are other issues too, where it looks like the VHDL may be more correct.

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Hi Dave,

Sorry for the delay. We have updated the VHDL model of S29CL032J. Please find it attached with this response.

Thanks and Regards,

Sudheesh

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SudheeshK
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Hi,

We recommend to use datasheets for the correct information about our parts.

Could you please provide more details about the issue that you face with VHDL model?

Thanks and Regards,

Sudheesh

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Well, as I said, the data sheet discusses the DQ5 status bit for error reporting throughout sections 7.7 and 7.8 of the datasheet. It would be acceptable for the VHDL (and Verilog) model files not to include this behaviour if this was a clearly stated limitation.

As an example of the other discrepancies that I have found, the VHDL model would suggest that footnote 112 applies to many more of the commands shown in Table 35 than it is shown against, meaning that most require a reset command to return the chip to normal operation. The VHDL model also shows that the "Unlock Bypass" mode of operation also supports the sector erase command in addition to the "Unlock Bypass [chip] Erase" command shown in Table 34. (And you'll note my clarification here, because it is not at all clear which type of erase is being called up here until you match up the op-code with the normal operation chip erase command's op-code, being 10h.)

I don't have any physical hardware to test, which is why I am highly reliant on the factual correctness of the datasheet and the formal behavioural VHDL model of the chip to get my software specification right.

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Any further comment from Cypress on this issue?

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Hi Dave,

Sorry for the delay. We have updated the VHDL model of S29CL032J. Please find it attached with this response.

Thanks and Regards,

Sudheesh

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