We recommend to use datasheets for the correct information about our parts.
Could you please provide more details about the issue that you face with VHDL model?
Thanks and Regards,
Well, as I said, the data sheet discusses the DQ5 status bit for error reporting throughout sections 7.7 and 7.8 of the datasheet. It would be acceptable for the VHDL (and Verilog) model files not to include this behaviour if this was a clearly stated limitation.
As an example of the other discrepancies that I have found, the VHDL model would suggest that footnote 112 applies to many more of the commands shown in Table 35 than it is shown against, meaning that most require a reset command to return the chip to normal operation. The VHDL model also shows that the "Unlock Bypass" mode of operation also supports the sector erase command in addition to the "Unlock Bypass [chip] Erase" command shown in Table 34. (And you'll note my clarification here, because it is not at all clear which type of erase is being called up here until you match up the op-code with the normal operation chip erase command's op-code, being 10h.)
I don't have any physical hardware to test, which is why I am highly reliant on the factual correctness of the datasheet and the formal behavioural VHDL model of the chip to get my software specification right.
Any further comment from Cypress on this issue?