The FX3 flags require 2 clock cycles to assert/de-assert the flag after the DMA is ready to receive/transfer data. To avoid this problem, you can use the DMA watermark flag along with the DMA_Thread0_Ready flag to identify the exact completion of transfer.
Please refer to AN65974 for details on using the DMA Watermark flag.
I d'not know how to set watermark value in "CyU3PGpifSocketConfigure (0,CY_U3P_PIB_SOCKET_0, 4 ,CyFalse,1).
uint16_t watermark, /**< Watermark level for this socket in number of 4-byte words. */
1.What is the meaning of 4-byte word.? if I give 4 as watermark at what clock period Flag will assert?.
2.The polarity of flag is changing when I give active low it assert at active high. how to give polarity of Flag signal?
With Best Regards,
I assume that you are using the FX3 as the slave and the external device as the master. Please correct me if I am wrong.
- When the watermark is set to 4 on a 16-bit bus width slave FIFO interface, the number of clock cycles the SLRD# can be left asserted is given by the below formula as '5'. Please refer to section 8.3 of the AN65974 application note.
watermark x (32/bus width) – 3
- Double click on the FLAG name in the GPIF II designer and you can change the polarity of the flag.