It looks like the SCL will always be driven low. The reason being all the SCL and SDA lines of I2C are expected to be at 'open drain drives low' drive mode. So, once the I2C line is pulled low, it stays low forever and acts as a permanent latch.
I'm afraid the switching functionality could not be achieved by a simple schematic. However, a custom verilog component could be developed to act as an I2C mux. It basically snoops the I2C packets from the master and decides how to connect the buses. I have attached the project. Please use it as reference.
Currently, the component assumes that the slave will not stretch the clock when individual data or address bits are sent by the master.
Similarly, it is assumed that the master will not stretch the clock when receiving individual bits from the slave.
In simple words, the component assumes that clock stretching will occur only during ACK/NACK phase and between bytes in a multi-byte transfer.
I hope this helps.
Thank you for sending the project. I will confirm weather it meet our requirement.