The timing of SSEL_out is different in different versions of SPI protocol. You can find the relating information in page 25-28 of datasheet.
I did see the three modes of operation,, however I didn't see any AC timing associated with the SSEL_out to first SCK Valid edge.
Also need the time from last clock to SSEL_out invalid.
A little more info,,
I'm trying to interface to an ADC with a USB-SPI bridge. The SPI chip select (SSEL) is also the start CONVERSION pin. All the solutions I've found have huge delays from SPI chip select and the first and last clocks.. I mean microseconds of time. It's killing my throughput...
May I know the ADC part number you use and your schematic? Indeed the datasheet did not give the time from SSEL to SCK, but it should not be longer than 1 SCLK.
1 SCLK would be great!.. I'm planing to use the https://www.analog.com/media/en/technical-documentation/data-sheets/233516f.pdf .
Don't want to post my full schematic be this is the SPI section of the ADC:
Right now I'm testing with a FDTI UNFT4222EV and Analog DC4212A-B development boards. Just made a cable to connect the two,,
Was about to send out PCB artwork before this timing issue popped up..
Today my CYUSBS234 should arrive and I'll send you some pictures of the setup and hold times...