- Have you passed the vendor command with the request 0xBB before reading data from the FX3?
- Is there any error code returned on the cyusb_bulk_transfer() function call? If yes, please mention the same.
- Before using the cyusb_bulk_transfer() function call, have you obtained the handle to the device, checked if the kernel driver is active and claimed the interface using the cyusb_gethandle(), cyusb_kernel_driver_active() and cyusb_claim_interface() function calls respectively.
EDIT: For reading data from the FPGA over to the USB interface, the slave interface must be configured and the SLWR#, ADR[1:0], PCLK must be driven by the FPGA(master). If there is no signalling on the GPIF II interface, the FPGA code has to be checked. The cyusb_bulk_transfer() function call on the IN endpoint reads the data that is present in the FX3 FIFO buffer.
1. Could you give me details about "passed the vendor command with the request 0xBB before reading data from the FX3".
2. There is no error code returned, it's locking up.
3. Before cyusb_bulk_transfer(), I've run cyusb_open(), cyusb_gethandle(), cyusb_kernel_driver_active(), cyusb_claim_interface(), from return value, all functions run sucessfully as below.
cyusb_open return: r = 1
cyusb_gethandle return: h1 = 4b4
cypress chipset detected
Successfully claimed interface
4. I've done an experiment, set GPIF RD_START as FSM reset state. After reset, I can see FX3 starts reading data from FPGA. Basically FPGA is working fine, if FX3 can start reading process.
Now need to figure out why RD_START state is never reached.