0 Replies Latest reply on Nov 27, 2018 6:01 AM by user_455868498

    UART Asynchronous PSoC Interface tips

    user_455868498

      This post attempts to address five questions that arose during the creation of an asynchronous interface in PSoC.

      Random errors were eliminated by changing parameters without a clear explanation provided.

      To those reading this, please add any references, links or comments that will help designers understand the details of asynchronous systems, how to minimize the chance for errors to propagate and build robust designs using minimal resources using PSoC components.

       

      An RS485 interface was created in two PSoC 5 based systems, one as Master, the other Slave:

      RS485 Master

      UART: 115200 baud, 1 start, 1 stop bit, UART Rx pin configured in “double-sync” mode.

      CPU:  CY8C5888AXQ-LP096

      System clock: 30 MHz

      IDE: PSoC Creator 4.1

       

      RS485 Slave

      UART: 115200 baud, 1 start, 1 stop bit, UART Rx pin configured in “transparent” mode

      CPU:  CY8C5868AXI-LP035

      System clock: 4 MHz

      IDE: PSoC Creator 4.1

       

      When using the 4-byte HW FIFO configuration with the “Internal Interrupt” on the RS485 Slave board, there were occasional missed bytes on the Slave receiver and the UART would show overrun flag active. The issue went away with any one of the following three changes to the Slave board’s configuration:

      1. Changed the Slave UART Rx pin to double sync. 

      a) Why is double-sync required of external pins when connected to a UART? When the UART is connected internally, there is no double-sync setting. 

      b) When should double-sync be used?

      2. Maintained transparent Rx Pin mode and changed to a 5-byte FIFO that implements a SW-based buffer and an “External Interrupt”. 

      c) What is the difference between these two FIFO designs and why does one work better than the other?

      3. Maintained transparent Rx Pin mode and increased the System Clock to 12MHz. 

      d) Why does a faster system clock affect this outcome?

       

      For all tests, the Master transmitter is sending bytes at 115200 baud using the PSoC RS485 library functions, and with the oscilloscope they can see there isn’t any inter-byte delay applied to the TX frame. 

                  e) Is there any inter-byte delay recommended (or not recommended) for this library?

       

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      The following thoughts are intended to help address the five questions above:

      A) Double sync filters out noise and prevents metastable states by clocking external signals through buffer registers so their value as presented to internal PSoC logic changes only on PSoC System clock boundaries. This is opposite of “Transparent” mode that implies the passing of raw asynchronous external signals directly to internal logic.

       

      B) Double sync should be used when signals switching near the rate of asynchronous clocks are shared between systems. Note that UART signals are typically switching at a rate much slower than the system clock. Double syncing adds integrity to signals at the expense of a slight delay and use of resources – a couple registers.

       

      C) Three changes are noted here: Increasing FIFO over 4-bytes, SW based buffers and External interrupts

        • Increasing the FIFO over 4-bytes utilizes interrupts that changes the dynamics of the UART implementation – reference “RX Buffer Size” on page 10 of the UART component data sheet @ http://www.cypress.com/documentation/component-datasheets/universal-asynchronous-receiver-transmitter-uart.
        • SW based buffers will be slower than hardware buffers. All data into a software buffer will be synchronized with the system clock, which dictates the cadence that software commands are performed.
        • External interrupts will by definition be slower. Internal interrupts could induce race conditions in cases where the interrupt is triggered before a process is complete. Interrupt handling should be analyzed at a system level to allow critical processes to complete in a timely fashion.

       

      D) System clock timing issues are described as %ERR – reference %ERR calculation in UART Component Datasheet rev D page 50 @ http://www.cypress.com/documentation/component-datasheets/universal-asynchronous-receiver-transmitter-uart

       

      E) I am not aware of any general inter-byte delay recommended. The implementation should be analyzed to ensure buffer space is available before data is transmitted.

       

      Some additional information may be found in related posts on Cypress Community:

      Problem with changing PSoC CPU clock @ https://community.cypress.com/message/147645#147645

      PSoC5LP UART receiver with a RX buffer > 4 bytes @ https://community.cypress.com/message/100334#100334