Yes, you can change SLWR,SLOE,PKEND pins polarity using GPIF-II Designer Tool.
To configure SLWR pin as a active high,right-click on the SLWR in the I/O Matrix Configuration diagram,click Input Signal Settings. as shown in the following figure.
Polarity: The assertion from the state machine can make the signal low or high depending on this setting.
I am getting Data (incremental data) from FPGA as a master and Cypress as 8 bit slave FIFO.
Given configuration as flow,
#define CY_FX_FIFOLP_DMA_BUF_COUNT (8)
#define CY_FX_FIFOLP_DMA_RX_SIZE (0)
dmaCfg.prodSckId = CY_U3P_PIB_SOCKET_0 ;
dmaCfg.consSckId =CY_U3P_UIB_SOCKET_CONS_2 ;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoPtoU, CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
In Every 512 bytes of data 16 bytes are missing in a DMA buffer. I Getting 0x0000 to 0x00FF ( in first buffer) and 0x0114 to 0x0213( second buffer) I between 2 - 512 bytes if data 16 bytes is missing. I attached the control center Receiving data screen shot.
With Best Regards,