1 Reply Latest reply on Nov 22, 2018 11:24 PM by keaj

    Receiving a Zero-Length Packet for every Short Packet, Why?

    ian.cam57_3441841

      Hi,

       

      I'm transferring data between my FPGA and the FX3 using the GPIF interface, I'm making bulk transfers with DMA Buffers of 1024 bytes, there's no problems here.

       

      Now, I'm trying to make short packet transfers (with short packets I mean that the DMA buffers sometimes are not completely full and I'd like to transfer the data in the buffer partialy full). I'm using the COMMIT action in the GPIF designer for this and using the Cypress Control Center Application for testing, actually, I'm receiving the short packets but for every short packet received I'm also receiving a Zero Packet.

       

      Can anyone tell me why is that?  It can be avoided? If yes, how?

       

      I think is important to say that in my interface the FX3 is the master and the FPGA is the slave, I'm using AUTO DMA Channels between the P-Ports and the USB-Ports and for now I'm just trying with Read Transfers (this mean a FIFO is partialy full in the FPGA and the FX3 is supposed to read it).

       

      Thanks!

       

      Ian.